Lines Matching +full:0 +full:x18c
33 #define DA8XX_CP_INTC_BASE 0xfffee000
37 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
39 #define DA8XX_JTAG_ID_REG 0x18
40 #define DA8XX_HOST1CFG_REG 0x44
41 #define DA8XX_CHIPSIG_REG 0x174
42 #define DA8XX_CFGCHIP0_REG 0x17c
43 #define DA8XX_CFGCHIP1_REG 0x180
44 #define DA8XX_CFGCHIP2_REG 0x184
45 #define DA8XX_CFGCHIP3_REG 0x188
46 #define DA8XX_CFGCHIP4_REG 0x18c
48 #define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
50 #define DA8XX_DEEPSLEEP_REG 0x8
51 #define DA8XX_PWRDN_REG 0x18
53 #define DA8XX_PSC0_BASE 0x01c10000
54 #define DA8XX_PLL0_BASE 0x01c11000
55 #define DA8XX_TIMER64P0_BASE 0x01c20000
56 #define DA8XX_TIMER64P1_BASE 0x01c21000
57 #define DA8XX_VPIF_BASE 0x01e17000
58 #define DA8XX_GPIO_BASE 0x01e26000
59 #define DA8XX_PSC1_BASE 0x01e27000
61 #define DA8XX_DSP_L2_RAM_BASE 0x11800000
62 #define DA8XX_DSP_L1P_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x600000)
63 #define DA8XX_DSP_L1D_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x700000)
65 #define DA8XX_AEMIF_CS2_BASE 0x60000000
66 #define DA8XX_AEMIF_CS3_BASE 0x62000000
67 #define DA8XX_AEMIF_CTL_BASE 0x68000000
68 #define DA8XX_SHARED_RAM_BASE 0x80000000
69 #define DA8XX_ARM_RAM_BASE 0xffff0000