Lines Matching +full:boot +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 #include <linux/irqchip/arm-gic-v3.h>
12 .arch armv7-a
16 * For the kernel proper, we need to find out the CPU boot mode long after
17 * boot, so we need to store it in a writable variable.
19 * This is not in .bss, because we set it sufficiently early that the boot-time
29 * Save the primary CPU boot mode. Requires 2 scratch registers.
38 * Compare the current mode with the one saved on the primary CPU.
43 .macro compare_cpu_mode_with_primary mode, reg1, reg2
46 cmp \mode, \reg1 @ matches primary CPU boot mode?
57 * The zImage loader only runs on one CPU, so we don't bother with mult-CPU
60 .macro compare_cpu_mode_with_primary mode, reg1, reg2
61 cmp \mode, \mode
69 * These must be called with the MMU and D-cache off.
86 * If the secondary has booted with a different mode, give up
94 * stub hypervisor on the remaining ones: because the saved boot mode
95 * is modified, it can't compare equal to the CPSR mode field any
102 retne lr @ give up if the CPU is not in HYP mode
108 * Eventually, CPU-specific code might be needed -- assume not for now
132 @ Make sure NS-SVC is initialised appropriately
187 bx lr @ The boot CPU mode is left in r4.