Lines Matching +full:bl +full:- +full:data +full:- +full:offset
1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/asm-offsets.h>
9 #include <asm/uaccess-asm.h>
13 @ -----------------
59 * ARMv7-M exception entry/exit macros.
86 @ we cannot rely on r0-r3 and r12 matching the value saved in the
87 @ exception frame because of tail-chaining. So these have to be
89 ldmia r12!, {r0-r3}
94 sub sp, #PT_REGS_SIZE-S_IP
95 stmdb sp!, {r0-r11}
98 @ r0-r7 are used for signals and never touched from now on. Clobbering
99 @ r8-r12 is OK.
101 ldmia r9!, {r8, r10-r12}
106 @ The cpu might automatically 8-byte align the stack. Bit 9
108 @ another 32-bit value is included in the stack.
116 @ store r13-r15, xPSR
117 stmia r8!, {r9-r12}
135 ldmia r12, {r1-r5}
137 @ an exception frame is always 8-byte aligned. To tell the hardware if
150 stmdb r2!, {r1, r3-r5}
151 ldmia sp, {r1, r3-r5}
153 stmdb r2!, {r0, r3-r5}
155 stmdb r2!, {r1, r3-r5}
161 @ restore original r4-r11
162 ldmia sp!, {r0-r11}
165 add sp, sp, #PT_REGS_SIZE-S_IP
174 @ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
177 .macro store_user_sp_lr, rd, rtemp, offset = 0 argument
182 str sp, [\rd, #\offset] @ save sp_usr
183 str lr, [\rd, #\offset + 4] @ save lr_usr
189 .macro load_user_sp_lr, rd, rtemp, offset = 0 argument
194 ldr sp, [\rd, #\offset] @ load sp_usr
195 ldr lr, [\rd, #\offset + 4] @ load lr_usr
208 bl trace_hardirqs_on
211 @ IRQs off again before pulling preserved data off the stack
226 @ We must avoid clrex due to Cortex-A15 erratum #830321
230 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
236 @ We must avoid clrex due to Cortex-A15 erratum #830321
240 ldmia sp, {r0 - r12}
248 @ svc_exit_via_fiq - like svc_exit but switches to FIQ mode before exit
259 @ supplied rpsr. This is because the FIQ exceptions are not re-entrant
268 ldmib r0, {r1 - r14} @ abort is deadly from here onward (it will
282 ldmia r0, {r2 - r12}
287 ldmia r0, {r0 - r1}
293 .macro restore_user_regs, fast = 0, offset = 0
312 ldr r1, [r2, #\offset + S_PSR] @ get calling cpsr
313 ldr lr, [r2, #\offset + S_PC]! @ get pc
318 @ We must avoid clrex due to Cortex-A15 erratum #830321
322 ldmdb r2, {r1 - lr}^ @ get calling r1 - lr
324 ldmdb r2, {r0 - lr}^ @ get calling r0 - lr
328 add sp, sp, #\offset + PT_REGS_SIZE
335 .if \offset
336 add sp, #\offset
342 load_user_sp_lr r2, r3, \offset + S_SP @ calling sp, lr
343 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
344 ldr lr, [sp, #\offset + S_PC] @ get pc
345 add sp, sp, #\offset + S_SP
350 @ We must avoid clrex due to Cortex-A15 erratum #830321
354 ldmdb sp, {r1 - r12} @ get calling r1 - r12
356 ldmdb sp, {r0 - r12} @ get calling r0 - r12
358 add sp, sp, #PT_REGS_SIZE - S_SP
371 stmdb sp!, {r0-r3, ip, lr}
372 bl user_exit_callable
373 ldmia sp!, {r0-r3, ip, lr}
375 bl user_exit_callable
383 stmdb sp!, {r0-r3, ip, lr}
384 bl user_enter_callable
385 ldmia sp!, {r0-r3, ip, lr}
387 bl user_enter_callable
401 ldmiacc r1, {r0 - r6} @ reload r0-r6
410 ldmiacc r1, {r0 - r6} @ reload r0-r6
419 * have in theory up to 7 arguments to a function - r0 to r6.