Lines Matching +full:0 +full:x7000e400
21 #define TEGRA_CLK_RESET_BASE 0x60006000
22 #define TEGRA_APB_MISC_BASE 0x70000000
23 #define TEGRA_UARTA_BASE 0x70006000
24 #define TEGRA_UARTB_BASE 0x70006040
25 #define TEGRA_UARTC_BASE 0x70006200
26 #define TEGRA_UARTD_BASE 0x70006300
27 #define TEGRA_UARTE_BASE 0x70006400
28 #define TEGRA_PMC_BASE 0x7000e400
30 #define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
31 #define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
32 #define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c)
33 #define TEGRA_CLK_OUT_ENB_L (TEGRA_CLK_RESET_BASE + 0x10)
34 #define TEGRA_CLK_OUT_ENB_H (TEGRA_CLK_RESET_BASE + 0x14)
35 #define TEGRA_CLK_OUT_ENB_U (TEGRA_CLK_RESET_BASE + 0x18)
36 #define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0)
37 #define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
43 #define UART_VIRTUAL_BASE 0xfe800000
49 ldr rp, [rp, #0] ; \
57 ldr rp, [rp, #0] ; \
76 mov \rv, #0 @ yes; record init is done
82 ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
91 cmp \rv, #0 @ UART 0?
136 90: mov \rp, #0
141 cmp \rp, #0 @ Valid UART address?
143 str \rp, [\tmp, #8] @ Store 0 in tegra_uart_virt
145 92: and \rv, \rp, #0xffffff @ offset within 1MB section
174 .word 0
176 .word 0
193 cmp \rx, #0
199 cmp \rx, #0
209 cmp \rx, #0