Lines Matching +full:0 +full:x25c
5 #define V7M_SCS_ICTR IOMEM(0xe000e004)
6 #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
10 #define V7M_SCB_CPUID 0x00
12 #define V7M_SCB_ICSR 0x04
16 #define V7M_SCB_ICSR_VECTACTIVE 0x000001ff
18 #define V7M_SCB_VTOR 0x08
20 #define V7M_SCB_AIRCR 0x0c
21 #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
24 #define V7M_SCB_SCR 0x10
27 #define V7M_SCB_CCR 0x14
33 #define V7M_SCB_SHPR2 0x1c
34 #define V7M_SCB_SHPR3 0x20
36 #define V7M_SCB_SHCSR 0x24
41 #define V7M_xPSR_FRAMEPTRALIGN 0x00000200
45 * When branching to an address that has bits [31:28] == 0xf an exception return
49 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
50 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
52 #define EXC_RET_STACK_MASK 0x00000004
57 #define V7M_SCB_CLIDR 0x78 /* Cache Level ID register */
58 #define V7M_SCB_CTR 0x7c /* Cache Type register */
59 #define V7M_SCB_CCSIDR 0x80 /* Cache size ID register */
60 #define V7M_SCB_CSSELR 0x84 /* Cache size selection register */
63 #define MPU_TYPE 0x90
64 #define MPU_CTRL 0x94
68 #define PMSAv7_RNR 0x98
69 #define PMSAv7_RBAR 0x9c
70 #define PMSAv7_RASR 0xa0
72 #define PMSAv8_RNR 0x98
73 #define PMSAv8_RBAR 0x9c
74 #define PMSAv8_RLAR 0xa0
77 #define PMSAv8_MAIR0 0xc0
78 #define PMSAv8_MAIR1 0xc4
81 #define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */
82 #define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */
83 #define V7M_SCB_DCIMVAC 0x25c /* D-cache invalidate by MVA to PoC */
84 #define V7M_SCB_DCISW 0x260 /* D-cache invalidate by set-way */
85 #define V7M_SCB_DCCMVAU 0x264 /* D-cache clean by MVA to PoU */
86 #define V7M_SCB_DCCMVAC 0x268 /* D-cache clean by MVA to PoC */
87 #define V7M_SCB_DCCSW 0x26c /* D-cache clean by set-way */
88 #define V7M_SCB_DCCIMVAC 0x270 /* D-cache clean and invalidate by MVA to PoC */
89 #define V7M_SCB_DCCISW 0x274 /* D-cache clean and invalidate by set-way */
90 #define V7M_SCB_BPIALL 0x278 /* D-cache clean and invalidate by set-way */