Lines Matching +full:serial +full:- +full:state
1 /* SPDX-License-Identifier: GPL-2.0 */
7 * This file contains definitions for the SA-1111 Companion Chip.
8 * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
10 * Macro that calculates real address for registers in the SA-1111
50 * - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
51 * - The Feb 2001 errata (278260-010) says that the previous errata
52 * (278260-009) is wrong, and its bit actually 12, fixed in spec
53 * 278242-003.
54 * - The SA1111 manual (278242) says bit 12, but 0 to enable.
55 * - Reality is bit 13, 1 to enable.
56 * -- rmk
111 * Serial Audio Controller
114 * SACR0 Serial Audio Common Control Register
115 * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register
116 * SACR2 Serial Audio AC-link Control Register
117 * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register
118 * SASR1 Serial Audio AC-link Interface & FIFO Status Register
119 * SASCR Serial Audio Status Clear Register
122 * ACCAR AC-link Command Address Register
123 * ACCDR AC-link Command Data Register
124 * ACSAR AC-link Status Address Register
125 * ACSDR AC-link Status Data Register
126 * SADTCS Serial Audio DMA Transmit Control/Status Register
127 * SADTSA Serial Audio DMA Transmit Buffer Start Address A
128 * SADTCA Serial Audio DMA Transmit Buffer Count Register A
129 * SADTSB Serial Audio DMA Transmit Buffer Start Address B
130 * SADTCB Serial Audio DMA Transmit Buffer Count Register B
131 * SADRCS Serial Audio DMA Receive Control/Status Register
132 * SADRSA Serial Audio DMA Receive Buffer Start Address A
133 * SADRCA Serial Audio DMA Receive Buffer Count Register A
134 * SADRSB Serial Audio DMA Receive Buffer Start Address B
135 * SADRCB Serial Audio DMA Receive Buffer Count Register B
136 * SAITR Serial Audio Interrupt Test Register
137 * SADR Serial Audio Data Register (16 x 32-bit)
261 * General-Purpose I/O Interface
267 * PA_SSR GPIO Block A Sleep State
271 * PB_SSR GPIO Block B Sleep State
275 * PC_SSR GPIO Block C Sleep State
334 * WAKE_EN0 Wake-up source enable 0
335 * WAKE_EN1 Wake-up source enable 1
336 * WAKE_POL0 Wake-up polarity selection 0
337 * WAKE_POL1 Wake-up polarity selection 1
397 #define sa1111_get_drvdata(d) dev_get_drvdata(&(d)->dev)
398 #define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
409 #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
435 int irq_base; /* base for cascaded on-chip IRQs */