1 /* SPDX-License-Identifier: GPL-2.0 */
38 	unsigned long flags;  in ____atomic_set_bit()  local
39 	unsigned long mask = BIT_MASK(bit);  in ____atomic_set_bit()  local
43 	raw_local_irq_save(flags);  in ____atomic_set_bit()
44 	*p |= mask;  in ____atomic_set_bit()
45 	raw_local_irq_restore(flags);  in ____atomic_set_bit()
50 	unsigned long flags;  in ____atomic_clear_bit()  local
51 	unsigned long mask = BIT_MASK(bit);  in ____atomic_clear_bit()  local
55 	raw_local_irq_save(flags);  in ____atomic_clear_bit()
56 	*p &= ~mask;  in ____atomic_clear_bit()
57 	raw_local_irq_restore(flags);  in ____atomic_clear_bit()
62 	unsigned long flags;  in ____atomic_change_bit()  local
63 	unsigned long mask = BIT_MASK(bit);  in ____atomic_change_bit()  local
67 	raw_local_irq_save(flags);  in ____atomic_change_bit()
68 	*p ^= mask;  in ____atomic_change_bit()
69 	raw_local_irq_restore(flags);  in ____atomic_change_bit()
75 	unsigned long flags;  in ____atomic_test_and_set_bit()  local
77 	unsigned long mask = BIT_MASK(bit);  in ____atomic_test_and_set_bit()  local
81 	raw_local_irq_save(flags);  in ____atomic_test_and_set_bit()
83 	*p = res | mask;  in ____atomic_test_and_set_bit()
84 	raw_local_irq_restore(flags);  in ____atomic_test_and_set_bit()
86 	return (res & mask) != 0;  in ____atomic_test_and_set_bit()
92 	unsigned long flags;  in ____atomic_test_and_clear_bit()  local
94 	unsigned long mask = BIT_MASK(bit);  in ____atomic_test_and_clear_bit()  local
98 	raw_local_irq_save(flags);  in ____atomic_test_and_clear_bit()
100 	*p = res & ~mask;  in ____atomic_test_and_clear_bit()
101 	raw_local_irq_restore(flags);  in ____atomic_test_and_clear_bit()
103 	return (res & mask) != 0;  in ____atomic_test_and_clear_bit()
109 	unsigned long flags;  in ____atomic_test_and_change_bit()  local
111 	unsigned long mask = BIT_MASK(bit);  in ____atomic_test_and_change_bit()  local
115 	raw_local_irq_save(flags);  in ____atomic_test_and_change_bit()
117 	*p = res ^ mask;  in ____atomic_test_and_change_bit()
118 	raw_local_irq_restore(flags);  in ____atomic_test_and_change_bit()
120 	return (res & mask) != 0;  in ____atomic_test_and_change_bit()
123 #include <asm-generic/bitops/non-atomic.h>
126  *  A note about Endian-ness.
127  *  -------------------------
132  *          ------------ physical data bus bits -----------
137  * This means that reading a 32-bit word at address 0 returns the same
147  * Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0.
151  * Native endian assembly bitops.  nr = 0 -> word 0 bit 0.
161  * Little endian assembly bitops.  nr = 0 -> byte 0 bit 0.
170  * Big endian assembly bitops.  nr = 0 -> byte 3 bit 0.
180  * The __* form of bitops are non-atomic and may be reordered.
220 #include <asm-generic/bitops/__fls.h>
221 #include <asm-generic/bitops/__ffs.h>
222 #include <asm-generic/bitops/fls.h>
223 #include <asm-generic/bitops/ffs.h>
228  * On ARMv5 and above, the gcc built-ins may rely on the clz instruction
232 #include <asm-generic/bitops/builtin-__fls.h>
233 #include <asm-generic/bitops/builtin-__ffs.h>
234 #include <asm-generic/bitops/builtin-fls.h>
235 #include <asm-generic/bitops/builtin-ffs.h>
239 #include <asm-generic/bitops/ffz.h>
241 #include <asm-generic/bitops/fls64.h>
243 #include <asm-generic/bitops/sched.h>
244 #include <asm-generic/bitops/hweight.h>
245 #include <asm-generic/bitops/lock.h>
269 #include <asm-generic/bitops/le.h>
272  * Ext2 is defined to use little-endian byte ordering.
274 #include <asm-generic/bitops/ext2-atomic-setbit.h>