Lines Matching +full:big +full:- +full:endian

1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Big endian support: Copyright 2001, Nicolas Pitre
34 * First, the atomic bitops. These use native endian.
123 #include <asm-generic/bitops/non-atomic.h>
126 * A note about Endian-ness.
127 * -------------------------
129 * When the ARM is put into big endian mode via CR15, the processor
132 * ------------ physical data bus bits -----------
135 * big byte 0 byte 1 byte 2 byte 3
137 * This means that reading a 32-bit word at address 0 returns the same
138 * value irrespective of the endian mode bit.
141 * "Big Endian" mode. ARM Application Note 61 is applicable, and is
144 * The following assumes that the data bus connectivity for big endian
147 * Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0.
151 * Native endian assembly bitops. nr = 0 -> word 0 bit 0.
161 * Little endian assembly bitops. nr = 0 -> byte 0 bit 0.
170 * Big endian assembly bitops. nr = 0 -> byte 3 bit 0.
180 * The __* form of bitops are non-atomic and may be reordered.
189 * Native endian atomic definitions.
200 * These are the little endian, atomic definitions.
209 * These are the big endian, atomic definitions.
220 #include <asm-generic/bitops/__fls.h>
221 #include <asm-generic/bitops/__ffs.h>
222 #include <asm-generic/bitops/fls.h>
223 #include <asm-generic/bitops/ffs.h>
228 * On ARMv5 and above, the gcc built-ins may rely on the clz instruction
232 #include <asm-generic/bitops/builtin-__fls.h>
233 #include <asm-generic/bitops/builtin-__ffs.h>
234 #include <asm-generic/bitops/builtin-fls.h>
235 #include <asm-generic/bitops/builtin-ffs.h>
239 #include <asm-generic/bitops/ffz.h>
241 #include <asm-generic/bitops/fls64.h>
243 #include <asm-generic/bitops/sched.h>
244 #include <asm-generic/bitops/hweight.h>
245 #include <asm-generic/bitops/lock.h>
269 #include <asm-generic/bitops/le.h>
272 * Ext2 is defined to use little-endian byte ordering.
274 #include <asm-generic/bitops/ext2-atomic-setbit.h>