Lines Matching full:lo
634 vmovn.i64 $D3#lo,$D3
636 vmovn.i64 $D0#lo,$D0
638 vbic.i32 $D3#lo,#0xfc000000 @ &=0x03ffffff
640 vbic.i32 $D0#lo,#0xfc000000
642 vshrn.u64 $T0#lo,$D4,#26
643 vmovn.i64 $D4#lo,$D4
645 vmovn.i64 $D1#lo,$D1
647 vbic.i32 $D4#lo,#0xfc000000
648 vbic.i32 $D1#lo,#0xfc000000
650 vadd.i32 $D0#lo,$D0#lo,$T0#lo
651 vshl.u32 $T0#lo,$T0#lo,#2
652 vshrn.u64 $T1#lo,$D2,#26
653 vmovn.i64 $D2#lo,$D2
654 vadd.i32 $D0#lo,$D0#lo,$T0#lo @ h4 -> h0
655 vadd.i32 $D3#lo,$D3#lo,$T1#lo @ h2 -> h3
656 vbic.i32 $D2#lo,#0xfc000000
658 vshr.u32 $T0#lo,$D0#lo,#26
659 vbic.i32 $D0#lo,#0xfc000000
660 vshr.u32 $T1#lo,$D3#lo,#26
661 vbic.i32 $D3#lo,#0xfc000000
662 vadd.i32 $D1#lo,$D1#lo,$T0#lo @ h0 -> h1
663 vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
671 vtrn.32 $R0,$D0#lo @ r^2:r^1
672 vtrn.32 $R2,$D2#lo
673 vtrn.32 $R3,$D3#lo
674 vtrn.32 $R1,$D1#lo
675 vtrn.32 $R4,$D4#lo
700 vmov $R0,$D0#lo @ r^4:r^3
701 vshl.u32 $S1,$D1#lo,#2 @ *5
702 vmov $R1,$D1#lo
703 vshl.u32 $S2,$D2#lo,#2
704 vmov $R2,$D2#lo
705 vshl.u32 $S3,$D3#lo,#2
706 vmov $R3,$D3#lo
707 vshl.u32 $S4,$D4#lo,#2
708 vmov $R4,$D4#lo
709 vadd.i32 $S1,$S1,$D1#lo
710 vadd.i32 $S2,$S2,$D2#lo
711 vadd.i32 $S3,$S3,$D3#lo
712 vadd.i32 $S4,$S4,$D4#lo
751 veor $D0#lo,$D0#lo,$D0#lo
754 veor $D1#lo,$D1#lo,$D1#lo
757 veor $D2#lo,$D2#lo,$D2#lo
760 veor $D3#lo,$D3#lo,$D3#lo
763 veor $D4#lo,$D4#lo,$D4#lo
769 vmov.32 $D0#lo[0],r2
770 vmov.32 $D1#lo[0],r3
771 vmov.32 $D2#lo[0],r4
772 vmov.32 $D3#lo[0],r5
773 vmov.32 $D4#lo[0],r6
784 veor $D0#lo,$D0#lo,$D0#lo
785 veor $D1#lo,$D1#lo,$D1#lo
786 veor $D2#lo,$D2#lo,$D2#lo
787 veor $D3#lo,$D3#lo,$D3#lo
788 veor $D4#lo,$D4#lo,$D4#lo
789 vld4.32 {$D0#lo[0],$D1#lo[0],$D2#lo[0],$D3#lo[0]},[$ctx]!
791 vld1.32 {$D4#lo[0]},[$ctx]
800 vld4.32 {$H0#lo[0],$H1#lo[0],$H2#lo[0],$H3#lo[0]},[$inp]!
801 vmov.32 $H4#lo[0],$padbit
811 vsri.u32 $H4#lo,$H3#lo,#8 @ base 2^32 -> base 2^26
812 vshl.u32 $H3#lo,$H3#lo,#18
814 vsri.u32 $H3#lo,$H2#lo,#14
815 vshl.u32 $H2#lo,$H2#lo,#12
816 vadd.i32 $H4#hi,$H4#lo,$D4#lo @ add hash value and move to #hi
818 vbic.i32 $H3#lo,#0xfc000000
819 vsri.u32 $H2#lo,$H1#lo,#20
820 vshl.u32 $H1#lo,$H1#lo,#6
822 vbic.i32 $H2#lo,#0xfc000000
823 vsri.u32 $H1#lo,$H0#lo,#26
824 vadd.i32 $H3#hi,$H3#lo,$D3#lo
826 vbic.i32 $H0#lo,#0xfc000000
827 vbic.i32 $H1#lo,#0xfc000000
828 vadd.i32 $H2#hi,$H2#lo,$D2#lo
830 vadd.i32 $H0#hi,$H0#lo,$D0#lo
831 vadd.i32 $H1#hi,$H1#lo,$D1#lo
842 it lo
846 vld4.32 {$H0#lo,$H1#lo,$H2#lo,$H3#lo},[$inp] @ inp[0:1]
906 vadd.i32 $H2#lo,$H2#lo,$D2#lo @ accumulate inp[0:1]
908 vadd.i32 $H0#lo,$H0#lo,$D0#lo
910 vadd.i32 $H3#lo,$H3#lo,$D3#lo
913 vadd.i32 $H1#lo,$H1#lo,$D1#lo
916 vadd.i32 $H4#lo,$H4#lo,$D4#lo
920 it lo
951 vmlal.u32 $D3,$H3#lo,${R0}[0]
952 vmlal.u32 $D0,$H0#lo,${R0}[0]
953 vmlal.u32 $D4,$H4#lo,${R0}[0]
954 vmlal.u32 $D1,$H1#lo,${R0}[0]
955 vmlal.u32 $D2,$H2#lo,${R0}[0]
958 vmlal.u32 $D3,$H2#lo,${R1}[0]
959 vmlal.u32 $D0,$H4#lo,${S1}[0]
960 vmlal.u32 $D4,$H3#lo,${R1}[0]
961 vmlal.u32 $D1,$H0#lo,${R1}[0]
962 vmlal.u32 $D2,$H1#lo,${R1}[0]
964 vmlal.u32 $D3,$H1#lo,${R2}[0]
965 vmlal.u32 $D0,$H3#lo,${S2}[0]
966 vmlal.u32 $D4,$H2#lo,${R2}[0]
967 vmlal.u32 $D1,$H4#lo,${S2}[0]
968 vmlal.u32 $D2,$H0#lo,${R2}[0]
970 vmlal.u32 $D3,$H0#lo,${R3}[0]
971 vmlal.u32 $D0,$H2#lo,${S3}[0]
972 vmlal.u32 $D4,$H1#lo,${R3}[0]
973 vmlal.u32 $D1,$H3#lo,${S3}[0]
974 vmlal.u32 $D3,$H4#lo,${S4}[0]
976 vmlal.u32 $D2,$H4#lo,${S3}[0]
977 vmlal.u32 $D0,$H1#lo,${S4}[0]
978 vmlal.u32 $D4,$H0#lo,${R4}[0]
980 vmlal.u32 $D1,$H2#lo,${S4}[0]
981 vmlal.u32 $D2,$H3#lo,${S4}[0]
983 vld4.32 {$H0#lo,$H1#lo,$H2#lo,$H3#lo},[$inp] @ inp[0:1]
997 vmovn.i64 $D3#lo,$D3
999 vmovn.i64 $D0#lo,$D0
1001 vbic.i32 $D3#lo,#0xfc000000
1005 vbic.i32 $D0#lo,#0xfc000000
1007 vshrn.u64 $T0#lo,$D4,#26
1008 vmovn.i64 $D4#lo,$D4
1010 vmovn.i64 $D1#lo,$D1
1013 vbic.i32 $D4#lo,#0xfc000000
1015 vbic.i32 $D1#lo,#0xfc000000
1017 vadd.i32 $D0#lo,$D0#lo,$T0#lo
1018 vshl.u32 $T0#lo,$T0#lo,#2
1020 vshrn.u64 $T1#lo,$D2,#26
1021 vmovn.i64 $D2#lo,$D2
1022 vaddl.u32 $D0,$D0#lo,$T0#lo @ h4 -> h0 [widen for a sec]
1024 vadd.i32 $D3#lo,$D3#lo,$T1#lo @ h2 -> h3
1026 vbic.i32 $D2#lo,#0xfc000000
1029 vshrn.u64 $T0#lo,$D0,#26 @ re-narrow
1030 vmovn.i64 $D0#lo,$D0
1033 vshr.u32 $T1#lo,$D3#lo,#26
1034 vbic.i32 $D3#lo,#0xfc000000
1035 vbic.i32 $D0#lo,#0xfc000000
1036 vadd.i32 $D1#lo,$D1#lo,$T0#lo @ h0 -> h1
1037 vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
1053 vadd.i32 $H2#hi,$H2#lo,$D2#lo @ add hash value and move to #hi
1054 vadd.i32 $H0#hi,$H0#lo,$D0#lo
1055 vadd.i32 $H3#hi,$H3#lo,$D3#lo
1056 vadd.i32 $H1#hi,$H1#lo,$D1#lo
1057 vadd.i32 $H4#hi,$H4#lo,$D4#lo
1063 vadd.i32 $H2#lo,$H2#lo,$D2#lo @ can be redundant
1065 vadd.i32 $H0#lo,$H0#lo,$D0#lo
1067 vadd.i32 $H3#lo,$H3#lo,$D3#lo
1069 vadd.i32 $H1#lo,$H1#lo,$D1#lo
1071 vadd.i32 $H4#lo,$H4#lo,$D4#lo
1116 vmlal.u32 $D2,$H2#lo,$R0
1117 vmlal.u32 $D0,$H0#lo,$R0
1118 vmlal.u32 $D3,$H3#lo,$R0
1119 vmlal.u32 $D1,$H1#lo,$R0
1120 vmlal.u32 $D4,$H4#lo,$R0
1122 vmlal.u32 $D0,$H4#lo,$S1
1124 vmlal.u32 $D3,$H2#lo,$R1
1126 vmlal.u32 $D1,$H0#lo,$R1
1127 vmlal.u32 $D4,$H3#lo,$R1
1128 vmlal.u32 $D2,$H1#lo,$R1
1130 vmlal.u32 $D3,$H1#lo,$R2
1132 vmlal.u32 $D0,$H3#lo,$S2
1134 vmlal.u32 $D4,$H2#lo,$R2
1135 vmlal.u32 $D1,$H4#lo,$S2
1136 vmlal.u32 $D2,$H0#lo,$R2
1138 vmlal.u32 $D3,$H0#lo,$R3
1139 vmlal.u32 $D0,$H2#lo,$S3
1140 vmlal.u32 $D4,$H1#lo,$R3
1141 vmlal.u32 $D1,$H3#lo,$S3
1142 vmlal.u32 $D2,$H4#lo,$S3
1144 vmlal.u32 $D3,$H4#lo,$S4
1146 vmlal.u32 $D0,$H1#lo,$S4
1148 vmlal.u32 $D4,$H0#lo,$R4
1149 vmlal.u32 $D1,$H2#lo,$S4
1150 vmlal.u32 $D2,$H3#lo,$S4
1156 vadd.i64 $D3#lo,$D3#lo,$D3#hi
1157 vadd.i64 $D0#lo,$D0#lo,$D0#hi
1158 vadd.i64 $D4#lo,$D4#lo,$D4#hi
1159 vadd.i64 $D1#lo,$D1#lo,$D1#hi
1160 vadd.i64 $D2#lo,$D2#lo,$D2#hi
1198 vst4.32 {$D0#lo[0],$D1#lo[0],$D2#lo[0],$D3#lo[0]},[$ctx]!
1199 vst1.32 {$D4#lo[0]},[$ctx]
1230 s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo or