Lines Matching +full:zynq +full:- +full:devcfg +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 u-boot {
13 compatible = "u-boot,config";
14 bootscr-address = /bits/ 64 <0x3000000>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "arm,cortex-a9";
27 clock-latency = <1000>;
28 cpu0-supply = <®ulator_vccpint>;
29 operating-points = <
36 cpu1: cpu@1 {
37 compatible = "arm,cortex-a9";
39 reg = <1>;
44 fpga_full: fpga-region {
45 compatible = "fpga-region";
46 fpga-mgr = <&devcfg>;
47 #address-cells = <1>;
48 #size-cells = <1>;
53 compatible = "arm,cortex-a9-pmu";
55 interrupt-parent = <&intc>;
61 compatible = "regulator-fixed";
62 regulator-name = "VCCPINT";
63 regulator-min-microvolt = <1000000>;
64 regulator-max-microvolt = <1000000>;
65 regulator-boot-on;
66 regulator-always-on;
70 compatible = "arm,coresight-static-replicator";
72 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
74 out-ports {
75 #address-cells = <1>;
76 #size-cells = <0>;
82 remote-endpoint = <&tpiu_in_port>;
85 port@1 {
86 reg = <1>;
88 remote-endpoint = <&etb_in_port>;
92 in-ports {
96 remote-endpoint = <&funnel_out_port>;
103 bootph-all;
104 compatible = "simple-bus";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 interrupt-parent = <&intc>;
111 compatible = "xlnx,zynq-xadc-1.00.a";
114 interrupt-parent = <&intc>;
119 compatible = "xlnx,zynq-can-1.0";
122 clock-names = "can_clk", "pclk";
125 interrupt-parent = <&intc>;
126 tx-fifo-depth = <0x40>;
127 rx-fifo-depth = <0x40>;
131 compatible = "xlnx,zynq-can-1.0";
134 clock-names = "can_clk", "pclk";
137 interrupt-parent = <&intc>;
138 tx-fifo-depth = <0x40>;
139 rx-fifo-depth = <0x40>;
143 compatible = "xlnx,zynq-gpio-1.0";
144 #gpio-cells = <2>;
146 gpio-controller;
147 interrupt-controller;
148 #interrupt-cells = <2>;
149 interrupt-parent = <&intc>;
155 compatible = "cdns,i2c-r1p10";
158 interrupt-parent = <&intc>;
160 clock-frequency = <400000>;
162 #address-cells = <1>;
163 #size-cells = <0>;
167 compatible = "cdns,i2c-r1p10";
170 interrupt-parent = <&intc>;
172 clock-frequency = <400000>;
174 #address-cells = <1>;
175 #size-cells = <0>;
178 intc: interrupt-controller@f8f01000 {
179 compatible = "arm,cortex-a9-gic";
180 #interrupt-cells = <3>;
181 interrupt-controller;
186 L2: cache-controller@f8f02000 {
187 compatible = "arm,pl310-cache";
190 arm,data-latency = <3 2 2>;
191 arm,tag-latency = <2 2 2>;
192 cache-unified;
193 cache-level = <2>;
196 mc: memory-controller@f8006000 {
197 compatible = "xlnx,zynq-ddrc-a05";
202 compatible = "mmio-sram";
204 #address-cells = <1>;
205 #size-cells = <1>;
207 ocm-sram@0 {
213 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
216 clock-names = "uart_clk", "pclk";
222 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
225 clock-names = "uart_clk", "pclk";
231 compatible = "xlnx,zynq-spi-r1p6";
234 interrupt-parent = <&intc>;
237 clock-names = "ref_clk", "pclk";
238 #address-cells = <1>;
239 #size-cells = <0>;
243 compatible = "xlnx,zynq-spi-r1p6";
246 interrupt-parent = <&intc>;
249 clock-names = "ref_clk", "pclk";
250 #address-cells = <1>;
251 #size-cells = <0>;
255 compatible = "xlnx,zynq-qspi-1.0";
257 interrupt-parent = <&intc>;
260 clock-names = "ref_clk", "pclk";
262 #address-cells = <1>;
263 #size-cells = <0>;
267 compatible = "xlnx,zynq-gem", "cdns,gem";
272 clock-names = "pclk", "hclk", "tx_clk";
273 #address-cells = <1>;
274 #size-cells = <0>;
278 compatible = "xlnx,zynq-gem", "cdns,gem";
283 clock-names = "pclk", "hclk", "tx_clk";
284 #address-cells = <1>;
285 #size-cells = <0>;
288 smcc: memory-controller@e000e000 {
289 compatible = "arm,pl353-smc-r2p1", "arm,primecell";
292 clock-names = "memclk", "apb_pclk";
297 #address-cells = <2>;
298 #size-cells = <1>;
299 interrupt-parent = <&intc>;
302 nfc0: nand-controller@0,0 {
303 compatible = "arm,pl353-nand-r2p1";
307 nor0: flash@1,0 {
309 compatible = "cfi-flash";
310 reg = <1 0 0x2000000>;
315 compatible = "arasan,sdhci-8.9a";
317 clock-names = "clk_xin", "clk_ahb";
319 interrupt-parent = <&intc>;
325 compatible = "arasan,sdhci-8.9a";
327 clock-names = "clk_xin", "clk_ahb";
329 interrupt-parent = <&intc>;
335 bootph-all;
336 #address-cells = <1>;
337 #size-cells = <1>;
338 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
342 bootph-all;
343 #clock-cells = <1>;
344 compatible = "xlnx,ps7-clkc";
345 fclk-enable = <0>;
346 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
361 compatible = "xlnx,zynq-reset";
363 #reset-cells = <1>;
368 compatible = "xlnx,pinctrl-zynq";
374 dmac_s: dma-controller@f8003000 {
377 interrupt-parent = <&intc>;
379 * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
387 #dma-cells = <1>;
389 clock-names = "apb_pclk";
392 devcfg: devcfg@f8007000 { label
393 compatible = "xlnx,zynq-devcfg-1.0";
395 interrupt-parent = <&intc>;
398 clock-names = "ref_clk";
403 compatible = "arm,cortex-a9-global-timer";
405 interrupts = <1 11 0x301>;
406 interrupt-parent = <&intc>;
411 interrupt-parent = <&intc>;
419 interrupt-parent = <&intc>;
427 bootph-all;
428 interrupt-parent = <&intc>;
429 interrupts = <1 13 0x301>;
430 compatible = "arm,cortex-a9-twd-timer";
436 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
439 interrupt-parent = <&intc>;
446 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
449 interrupt-parent = <&intc>;
457 compatible = "cdns,wdt-r1p2";
458 interrupt-parent = <&intc>;
459 interrupts = <0 9 1>;
461 timeout-sec = <10>;
465 compatible = "arm,coresight-etb10", "arm,primecell";
468 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
469 in-ports {
472 remote-endpoint = <&replicator_out_port1>;
479 compatible = "arm,coresight-tpiu", "arm,primecell";
482 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
483 in-ports {
486 remote-endpoint = <&replicator_out_port0>;
493 compatible = "arm,coresight-static-funnel", "arm,primecell";
496 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
499 out-ports {
502 remote-endpoint =
508 in-ports {
509 #address-cells = <1>;
510 #size-cells = <0>;
516 remote-endpoint = <&ptm0_out_port>;
520 port@1 {
521 reg = <1>;
523 remote-endpoint = <&ptm1_out_port>;
537 compatible = "arm,coresight-etm3x", "arm,primecell";
540 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
542 out-ports {
545 remote-endpoint = <&funnel0_in_port0>;
552 compatible = "arm,coresight-etm3x", "arm,primecell";
555 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
557 out-ports {
560 remote-endpoint = <&funnel0_in_port1>;