Lines Matching +full:pl353 +full:- +full:nand +full:- +full:r2p1
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <®ulator_vccpint>;
22 operating-points = <
30 compatible = "arm,cortex-a9";
37 fpga_full: fpga-full {
38 compatible = "fpga-region";
39 fpga-mgr = <&devcfg>;
40 #address-cells = <1>;
41 #size-cells = <1>;
46 compatible = "arm,cortex-a9-pmu";
48 interrupt-parent = <&intc>;
54 compatible = "regulator-fixed";
55 regulator-name = "VCCPINT";
56 regulator-min-microvolt = <1000000>;
57 regulator-max-microvolt = <1000000>;
58 regulator-boot-on;
59 regulator-always-on;
63 compatible = "arm,coresight-static-replicator";
65 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
67 out-ports {
68 #address-cells = <1>;
69 #size-cells = <0>;
75 remote-endpoint = <&tpiu_in_port>;
81 remote-endpoint = <&etb_in_port>;
85 in-ports {
89 remote-endpoint = <&funnel_out_port>;
96 compatible = "simple-bus";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 interrupt-parent = <&intc>;
103 compatible = "xlnx,zynq-xadc-1.00.a";
106 interrupt-parent = <&intc>;
111 compatible = "xlnx,zynq-can-1.0";
114 clock-names = "can_clk", "pclk";
117 interrupt-parent = <&intc>;
118 tx-fifo-depth = <0x40>;
119 rx-fifo-depth = <0x40>;
123 compatible = "xlnx,zynq-can-1.0";
126 clock-names = "can_clk", "pclk";
129 interrupt-parent = <&intc>;
130 tx-fifo-depth = <0x40>;
131 rx-fifo-depth = <0x40>;
135 compatible = "xlnx,zynq-gpio-1.0";
136 #gpio-cells = <2>;
138 gpio-controller;
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 interrupt-parent = <&intc>;
147 compatible = "cdns,i2c-r1p10";
150 interrupt-parent = <&intc>;
152 clock-frequency = <400000>;
154 #address-cells = <1>;
155 #size-cells = <0>;
159 compatible = "cdns,i2c-r1p10";
162 interrupt-parent = <&intc>;
164 clock-frequency = <400000>;
166 #address-cells = <1>;
167 #size-cells = <0>;
170 intc: interrupt-controller@f8f01000 {
171 compatible = "arm,cortex-a9-gic";
172 #interrupt-cells = <3>;
173 interrupt-controller;
178 L2: cache-controller@f8f02000 {
179 compatible = "arm,pl310-cache";
182 arm,data-latency = <3 2 2>;
183 arm,tag-latency = <2 2 2>;
184 cache-unified;
185 cache-level = <2>;
188 mc: memory-controller@f8006000 {
189 compatible = "xlnx,zynq-ddrc-a05";
194 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
197 clock-names = "uart_clk", "pclk";
203 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
206 clock-names = "uart_clk", "pclk";
212 compatible = "xlnx,zynq-spi-r1p6";
215 interrupt-parent = <&intc>;
218 clock-names = "ref_clk", "pclk";
219 #address-cells = <1>;
220 #size-cells = <0>;
224 compatible = "xlnx,zynq-spi-r1p6";
227 interrupt-parent = <&intc>;
230 clock-names = "ref_clk", "pclk";
231 #address-cells = <1>;
232 #size-cells = <0>;
236 compatible = "xlnx,zynq-qspi-1.0";
238 interrupt-parent = <&intc>;
241 clock-names = "ref_clk", "pclk";
243 #address-cells = <1>;
244 #size-cells = <0>;
248 compatible = "xlnx,zynq-gem", "cdns,gem";
253 clock-names = "pclk", "hclk", "tx_clk";
254 #address-cells = <1>;
255 #size-cells = <0>;
259 compatible = "xlnx,zynq-gem", "cdns,gem";
264 clock-names = "pclk", "hclk", "tx_clk";
265 #address-cells = <1>;
266 #size-cells = <0>;
269 smcc: memory-controller@e000e000 {
270 compatible = "arm,pl353-smc-r2p1", "arm,primecell";
273 clock-names = "memclk", "apb_pclk";
275 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
278 #address-cells = <2>;
279 #size-cells = <1>;
281 nfc0: nand-controller@0,0 {
282 compatible = "arm,pl353-nand-r2p1";
285 #address-cells = <1>;
286 #size-cells = <0>;
291 compatible = "arasan,sdhci-8.9a";
293 clock-names = "clk_xin", "clk_ahb";
295 interrupt-parent = <&intc>;
301 compatible = "arasan,sdhci-8.9a";
303 clock-names = "clk_xin", "clk_ahb";
305 interrupt-parent = <&intc>;
311 #address-cells = <1>;
312 #size-cells = <1>;
313 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
317 #clock-cells = <1>;
318 compatible = "xlnx,ps7-clkc";
319 fclk-enable = <0>;
320 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
335 compatible = "xlnx,zynq-reset";
337 #reset-cells = <1>;
342 compatible = "xlnx,pinctrl-zynq";
348 dmac_s: dma-controller@f8003000 {
351 interrupt-parent = <&intc>;
353 * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
361 #dma-cells = <1>;
363 clock-names = "apb_pclk";
367 compatible = "xlnx,zynq-devcfg-1.0";
369 interrupt-parent = <&intc>;
372 clock-names = "ref_clk";
377 compatible = "arm,cortex-a9-global-timer";
380 interrupt-parent = <&intc>;
385 interrupt-parent = <&intc>;
393 interrupt-parent = <&intc>;
401 interrupt-parent = <&intc>;
403 compatible = "arm,cortex-a9-twd-timer";
409 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
412 interrupt-parent = <&intc>;
419 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
422 interrupt-parent = <&intc>;
430 compatible = "cdns,wdt-r1p2";
431 interrupt-parent = <&intc>;
434 timeout-sec = <10>;
438 compatible = "arm,coresight-etb10", "arm,primecell";
441 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
442 in-ports {
445 remote-endpoint = <&replicator_out_port1>;
452 compatible = "arm,coresight-tpiu", "arm,primecell";
455 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
456 in-ports {
459 remote-endpoint = <&replicator_out_port0>;
466 compatible = "arm,coresight-static-funnel", "arm,primecell";
469 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
472 out-ports {
475 remote-endpoint =
481 in-ports {
482 #address-cells = <1>;
483 #size-cells = <0>;
489 remote-endpoint = <&ptm0_out_port>;
496 remote-endpoint = <&ptm1_out_port>;
510 compatible = "arm,coresight-etm3x", "arm,primecell";
513 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
515 out-ports {
518 remote-endpoint = <&funnel0_in_port0>;
525 compatible = "arm,coresight-etm3x", "arm,primecell";
528 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
530 out-ports {
533 remote-endpoint = <&funnel0_in_port1>;