Lines Matching +full:0 +full:xe4000000
13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0>;
47 interrupts = <0 5 4>, <0 6 4>;
49 reg = <0xf8891000 0x1000>,
50 <0xf8893000 0x1000>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
104 reg = <0xf8007100 0x20>;
105 interrupts = <0 7 4>;
115 reg = <0xe0008000 0x1000>;
116 interrupts = <0 28 4>;
118 tx-fifo-depth = <0x40>;
119 rx-fifo-depth = <0x40>;
127 reg = <0xe0009000 0x1000>;
128 interrupts = <0 51 4>;
130 tx-fifo-depth = <0x40>;
131 rx-fifo-depth = <0x40>;
142 interrupts = <0 20 4>;
143 reg = <0xe000a000 0x1000>;
151 interrupts = <0 25 4>;
153 reg = <0xe0004000 0x1000>;
155 #size-cells = <0>;
163 interrupts = <0 48 4>;
165 reg = <0xe0005000 0x1000>;
167 #size-cells = <0>;
174 reg = <0xF8F01000 0x1000>,
175 <0xF8F00100 0x100>;
180 reg = <0xF8F02000 0x1000>;
181 interrupts = <0 2 4>;
190 reg = <0xf8006000 0x1000>;
198 reg = <0xE0000000 0x1000>;
199 interrupts = <0 27 4>;
207 reg = <0xE0001000 0x1000>;
208 interrupts = <0 50 4>;
213 reg = <0xe0006000 0x1000>;
216 interrupts = <0 26 4>;
220 #size-cells = <0>;
225 reg = <0xe0007000 0x1000>;
228 interrupts = <0 49 4>;
232 #size-cells = <0>;
237 reg = <0xe000d000 0x1000>;
239 interrupts = <0 19 4>;
244 #size-cells = <0>;
249 reg = <0xe000b000 0x1000>;
251 interrupts = <0 22 4>;
255 #size-cells = <0>;
260 reg = <0xe000c000 0x1000>;
262 interrupts = <0 45 4>;
266 #size-cells = <0>;
271 reg = <0xe000e000 0x0001000>;
275 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
276 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
277 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
281 nfc0: nand-controller@0,0 {
283 reg = <0 0 0x1000000>;
286 #size-cells = <0>;
296 interrupts = <0 24 4>;
297 reg = <0xe0100000 0x1000>;
306 interrupts = <0 47 4>;
307 reg = <0xe0101000 0x1000>;
314 reg = <0xF8000000 0x1000>;
319 fclk-enable = <0>;
331 reg = <0x100 0x100>;
336 reg = <0x200 0x48>;
343 reg = <0x700 0x200>;
350 reg = <0xf8003000 0x1000>;
356 interrupts = <0 13 4>,
357 <0 14 4>, <0 15 4>,
358 <0 16 4>, <0 17 4>,
359 <0 40 4>, <0 41 4>,
360 <0 42 4>, <0 43 4>;
368 reg = <0xf8007000 0x100>;
370 interrupts = <0 8 4>;
378 reg = <0xf8f00200 0x20>;
379 interrupts = <1 11 0x301>;
386 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
389 reg = <0xF8001000 0x1000>;
394 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
397 reg = <0xF8002000 0x1000>;
402 interrupts = <1 13 0x301>;
404 reg = <0xf8f00600 0x20>;
413 interrupts = <0 21 4>;
414 reg = <0xe0002000 0x1000>;
423 interrupts = <0 44 4>;
424 reg = <0xe0003000 0x1000>;
432 interrupts = <0 9 1>;
433 reg = <0xf8005000 0x1000>;
439 reg = <0xf8801000 0x1000>;
453 reg = <0xf8803000 0x1000>;
467 reg = <0xf8804000 0x1000>;
483 #size-cells = <0>;
486 port@0 {
487 reg = <0>;
511 reg = <0xf889c000 0x1000>;
526 reg = <0xf889d000 0x1000>;