Lines Matching +full:powervr +full:- +full:sgx544
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12 #include <dt-bindings/clock/omap5.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 interrupt-parent = <&wakeupgen>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a15";
52 operating-points = <
59 clock-names = "cpu";
61 clock-latency = <300000>; /* From omap-cpufreq driver */
64 #cooling-cells = <2>; /* min followed by max */
68 compatible = "arm,cortex-a15";
71 operating-points = <
78 clock-names = "cpu";
80 clock-latency = <300000>; /* From omap-cpufreq driver */
83 #cooling-cells = <2>; /* min followed by max */
87 thermal-zones {
88 #include "omap4-cpu-thermal.dtsi"
89 #include "omap5-gpu-thermal.dtsi"
90 #include "omap5-core-thermal.dtsi"
94 compatible = "arm,armv7-timer";
100 interrupt-parent = <&gic>;
104 compatible = "arm,cortex-a15-pmu";
111 * interconnect as simple-pm-bus probes at module_init() time.
114 compatible = "mmio-sram";
118 gic: interrupt-controller@48211000 {
119 compatible = "arm,cortex-a15-gic";
120 interrupt-controller;
121 #interrupt-cells = <3>;
126 interrupt-parent = <&gic>;
129 wakeupgen: interrupt-controller@48281000 {
130 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
131 interrupt-controller;
132 #interrupt-cells = <3>;
134 interrupt-parent = <&gic>;
145 compatible = "simple-pm-bus";
146 power-domains = <&prm_core>;
150 #address-cells = <1>;
151 #size-cells = <1>;
153 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
155 l3-noc@44000000 {
156 compatible = "ti,omap5-l3-noc";
173 target-module@48210000 {
174 compatible = "ti,sysc-omap4-simple", "ti,sysc";
175 power-domains = <&prm_mpu>;
177 clock-names = "fck";
178 #address-cells = <1>;
179 #size-cells = <1>;
183 compatible = "ti,omap4-mpu";
191 target-module@50000000 {
192 compatible = "ti,sysc-omap2", "ti,sysc";
196 reg-names = "rev", "sysc", "syss";
197 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
200 ti,syss-mask = <1>;
201 ti,no-idle-on-init;
203 clock-names = "fck";
204 #address-cells = <1>;
205 #size-cells = <1>;
210 compatible = "ti,omap4430-gpmc";
212 #address-cells = <2>;
213 #size-cells = <1>;
216 dma-names = "rxtx";
217 gpmc,num-cs = <8>;
218 gpmc,num-waitpins = <4>;
219 clock-names = "fck";
220 interrupt-controller;
221 #interrupt-cells = <2>;
222 gpio-controller;
223 #gpio-cells = <2>;
227 target-module@55082000 {
228 compatible = "ti,sysc-omap2", "ti,sysc";
232 reg-names = "rev", "sysc", "syss";
233 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
236 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
240 clock-names = "fck";
242 reset-names = "rstctrl";
244 #size-cells = <1>;
245 #address-cells = <1>;
248 compatible = "ti,omap4-iommu";
251 #iommu-cells = <0>;
252 ti,iommu-bus-err-back;
257 compatible = "ti,omap5-dsp";
262 firmware-name = "omap5-dsp-fw.xe64T";
268 compatible = "ti,omap5-ipu";
270 reg-names = "l2ram";
274 firmware-name = "omap5-ipu-fw.xem4";
279 target-module@4e000000 {
280 compatible = "ti,sysc-omap2", "ti,sysc";
283 reg-names = "rev", "sysc";
284 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
288 #size-cells = <1>;
289 #address-cells = <1>;
292 compatible = "ti,omap5-dmm";
298 target-module@4c000000 {
299 compatible = "ti,sysc-omap4-simple", "ti,sysc";
301 reg-names = "rev";
303 clock-names = "fck";
304 ti,no-idle;
305 #address-cells = <1>;
306 #size-cells = <1>;
310 compatible = "ti,emif-4d5";
313 phy-type = <2>; /* DDR PHY type: Intelli PHY */
314 hw-caps-read-idle-ctrl;
315 hw-caps-ll-interface;
316 hw-caps-temp-alert;
320 target-module@4d000000 {
321 compatible = "ti,sysc-omap4-simple", "ti,sysc";
323 reg-names = "rev";
325 clock-names = "fck";
326 ti,no-idle;
327 #address-cells = <1>;
328 #size-cells = <1>;
332 compatible = "ti,emif-4d5";
335 phy-type = <2>; /* DDR PHY type: Intelli PHY */
336 hw-caps-read-idle-ctrl;
337 hw-caps-ll-interface;
338 hw-caps-temp-alert;
342 aes1_target: target-module@4b501000 {
343 compatible = "ti,sysc-omap2", "ti,sysc";
347 reg-names = "rev", "sysc", "syss";
348 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
350 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
354 ti,syss-mask = <1>;
357 clock-names = "fck";
358 #address-cells = <1>;
359 #size-cells = <1>;
363 compatible = "ti,omap4-aes";
367 dma-names = "tx", "rx";
371 aes2_target: target-module@4b701000 {
372 compatible = "ti,sysc-omap2", "ti,sysc";
376 reg-names = "rev", "sysc", "syss";
377 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
379 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
383 ti,syss-mask = <1>;
386 clock-names = "fck";
387 #address-cells = <1>;
388 #size-cells = <1>;
392 compatible = "ti,omap4-aes";
396 dma-names = "tx", "rx";
400 sham_target: target-module@4b100000 {
401 compatible = "ti,sysc-omap3-sham", "ti,sysc";
405 reg-names = "rev", "sysc", "syss";
406 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
408 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
411 ti,syss-mask = <1>;
414 clock-names = "fck";
415 #address-cells = <1>;
416 #size-cells = <1>;
420 compatible = "ti,omap4-sham";
424 dma-names = "rx";
434 compatible = "ti,omap5430-bandgap";
436 #thermal-sensor-cells = <1>;
439 target-module@56000000 {
440 compatible = "ti,sysc-omap4", "ti,sysc";
443 reg-names = "rev", "sysc";
444 ti,sysc-midle = <SYSC_IDLE_FORCE>,
447 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
451 clock-names = "fck";
452 #address-cells = <1>;
453 #size-cells = <1>;
457 compatible = "ti,omap5432-gpu", "img,powervr-sgx544";
463 target-module@58000000 {
464 compatible = "ti,sysc-omap2", "ti,sysc";
467 reg-names = "rev", "syss";
468 ti,syss-mask = <1>;
469 power-domains = <&prm_dss>;
474 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
475 #address-cells = <1>;
476 #size-cells = <1>;
480 compatible = "ti,omap5-dss";
484 clock-names = "fck";
485 #address-cells = <1>;
486 #size-cells = <1>;
489 target-module@1000 {
490 compatible = "ti,sysc-omap2", "ti,sysc";
494 reg-names = "rev", "sysc", "syss";
495 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
498 ti,sysc-midle = <SYSC_IDLE_FORCE>,
501 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
505 ti,syss-mask = <1>;
507 clock-names = "fck";
508 #address-cells = <1>;
509 #size-cells = <1>;
513 compatible = "ti,omap5-dispc";
517 clock-names = "fck";
521 target-module@2000 {
522 compatible = "ti,sysc-omap2", "ti,sysc";
526 reg-names = "rev", "sysc", "syss";
527 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
530 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
532 ti,syss-mask = <1>;
534 clock-names = "fck";
535 #address-cells = <1>;
536 #size-cells = <1>;
540 compatible = "ti,omap5-rfbi";
544 clock-names = "fck", "ick";
548 target-module@4000 {
549 compatible = "ti,sysc-omap2", "ti,sysc";
553 reg-names = "rev", "sysc", "syss";
554 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
557 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
561 ti,syss-mask = <1>;
562 #address-cells = <1>;
563 #size-cells = <1>;
567 compatible = "ti,omap5-dsi";
571 reg-names = "proto", "phy", "pll";
576 clock-names = "fck", "sys_clk";
578 #address-cells = <1>;
579 #size-cells = <0>;
583 target-module@9000 {
584 compatible = "ti,sysc-omap2", "ti,sysc";
588 reg-names = "rev", "sysc", "syss";
589 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
592 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
596 ti,syss-mask = <1>;
597 #address-cells = <1>;
598 #size-cells = <1>;
602 compatible = "ti,omap5-dsi";
606 reg-names = "proto", "phy", "pll";
611 clock-names = "fck", "sys_clk";
613 #address-cells = <1>;
614 #size-cells = <0>;
618 target-module@40000 {
619 compatible = "ti,sysc-omap4", "ti,sysc";
622 reg-names = "rev", "sysc";
623 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
627 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
630 clock-names = "fck", "dss_clk";
631 #address-cells = <1>;
632 #size-cells = <1>;
636 compatible = "ti,omap5-hdmi";
641 reg-names = "wp", "pll", "phy", "core";
646 clock-names = "fck", "sys_clk";
648 dma-names = "audio_tx";
654 abb_mpu: regulator-abb-mpu {
655 compatible = "ti,abb-v2";
656 regulator-name = "abb_mpu";
657 #address-cells = <0>;
658 #size-cells = <0>;
660 ti,settling-time = <50>;
661 ti,clock-cycles = <16>;
665 reg-names = "base-address", "int-address",
666 "efuse-address", "ldo-address";
667 ti,tranxdone-status-mask = <0x80>;
669 ti,ldovbb-override-mask = <0x400>;
671 ti,ldovbb-vset-mask = <0x1F>;
684 abb_mm: regulator-abb-mm {
685 compatible = "ti,abb-v2";
686 regulator-name = "abb_mm";
687 #address-cells = <0>;
688 #size-cells = <0>;
690 ti,settling-time = <50>;
691 ti,clock-cycles = <16>;
695 reg-names = "base-address", "int-address",
696 "efuse-address", "ldo-address";
697 ti,tranxdone-status-mask = <0x80000000>;
699 ti,ldovbb-override-mask = <0x400>;
701 ti,ldovbb-vset-mask = <0x1F>;
717 polling-delay = <500>; /* milliseconds */
718 coefficients = <65 (-1791)>;
721 #include "omap5-l4.dtsi"
722 #include "omap54xx-clocks.dtsi"
725 coefficients = <117 (-2992)>;
732 #include "omap5-l4-abe.dtsi"
733 #include "omap54xx-clocks.dtsi"
737 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
739 #power-domain-cells = <0>;
743 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
745 #reset-cells = <1>;
746 #power-domain-cells = <0>;
750 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
752 #power-domain-cells = <0>;
756 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
758 #power-domain-cells = <0>;
762 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
764 #reset-cells = <1>;
765 #power-domain-cells = <0>;
769 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
771 #reset-cells = <1>;
772 #power-domain-cells = <0>;
776 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
778 #power-domain-cells = <0>;
782 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
784 #power-domain-cells = <0>;
788 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
790 #power-domain-cells = <0>;
794 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
796 #power-domain-cells = <0>;
800 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
802 #power-domain-cells = <0>;
806 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
808 #power-domain-cells = <0>;
812 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
814 #power-domain-cells = <0>;
818 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
820 #reset-cells = <1>;
824 /* Preferred always-on timer for clockevent */
826 ti,no-reset-on-init;
827 ti,no-idle;
829 assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
830 assigned-clock-parents = <&sys_32k_ck>;