Lines Matching +full:0 +full:x55020000
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
147 clocks = <&l3main1_clkctrl OMAP5_L3_MAIN_1_CLKCTRL 0>,
148 <&l3main2_clkctrl OMAP5_L3_MAIN_2_CLKCTRL 0>,
149 <&l3instr_clkctrl OMAP5_L3_MAIN_3_CLKCTRL 0>;
152 ranges = <0 0 0 0xc0000000>;
153 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
157 reg = <0x44000000 0x2000>,
158 <0x44800000 0x3000>,
159 <0x45000000 0x4000>;
176 clocks = <&mpu_clkctrl OMAP5_MPU_CLKCTRL 0>;
180 ranges = <0 0x48210000 0x1f0000>;
193 reg = <0x50000000 4>,
194 <0x50000010 4>,
195 <0x50000014 4>;
202 clocks = <&l3main2_clkctrl OMAP5_L3_MAIN_2_GPMC_CLKCTRL 0>;
206 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
207 <0x00000000 0x00000000 0x40000000>; /* data */
211 reg = <0x50000000 0x1000>;
229 reg = <0x55082000 0x4>,
230 <0x55082010 0x4>,
231 <0x55082014 0x4>;
239 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
243 ranges = <0x0 0x55082000 0x100>;
247 mmu_ipu: mmu@0 {
249 reg = <0x0 0x100>;
251 #iommu-cells = <0>;
258 ti,bootreg = <&scm_conf 0x304 0>;
260 resets = <&prm_dsp 0>;
261 clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
269 reg = <0x55020000 0x10000>;
272 resets = <&prm_core 0>, <&prm_core 1>;
273 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
281 reg = <0x4e000000 0x4>,
282 <0x4e000010 0x4>;
287 ranges = <0x0 0x4e000000 0x2000000>;
291 dmm@0 {
293 reg = <0 0x800>;
300 reg = <0x4c000000 0x4>;
302 clocks = <&emif_clkctrl OMAP5_EMIF1_CLKCTRL 0>;
307 ranges = <0x0 0x4c000000 0x1000000>;
309 emif1: emif@0 {
311 reg = <0 0x400>;
322 reg = <0x4d000000 0x4>;
324 clocks = <&emif_clkctrl OMAP5_EMIF2_CLKCTRL 0>;
329 ranges = <0x0 0x4d000000 0x1000000>;
331 emif2: emif@0 {
333 reg = <0 0x400>;
344 reg = <0x4b501080 0x4>,
345 <0x4b501084 0x4>,
346 <0x4b501088 0x4>;
356 clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
360 ranges = <0x0 0x4b501000 0x1000>;
362 aes1: aes@0 {
364 reg = <0 0xa0>;
373 reg = <0x4b701080 0x4>,
374 <0x4b701084 0x4>,
375 <0x4b701088 0x4>;
385 clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>;
389 ranges = <0x0 0x4b701000 0x1000>;
391 aes2: aes@0 {
393 reg = <0 0xa0>;
402 reg = <0x4b100100 0x4>,
403 <0x4b100110 0x4>,
404 <0x4b100114 0x4>;
413 clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
417 ranges = <0x0 0x4b100000 0x1000>;
419 sham: sham@0 {
421 reg = <0 0x300>;
429 reg = <0x4a0021e0 0xc
430 0x4a00232c 0xc
431 0x4a002380 0x2c
432 0x4a0023C0 0x3c>;
441 reg = <0x5600fe00 0x4>,
442 <0x5600fe10 0x4>;
450 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
454 ranges = <0 0x56000000 0x2000000>;
456 gpu@0 {
458 reg = <0x0 0x2000000>; /* 32MB */
465 reg = <0x58000000 4>,
466 <0x58000014 4>;
470 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
477 ranges = <0 0x58000000 0x1000000>;
479 dss: dss@0 {
481 reg = <0 0x80>;
487 ranges = <0 0 0x1000000>;
491 reg = <0x1000 0x4>,
492 <0x1010 0x4>,
493 <0x1014 0x4>;
510 ranges = <0 0x1000 0x1000>;
512 dispc@0 {
514 reg = <0 0x1000>;
523 reg = <0x2000 0x4>,
524 <0x2010 0x4>,
525 <0x2014 0x4>;
537 ranges = <0 0x2000 0x1000>;
539 rfbi: encoder@0 {
541 reg = <0 0x100>;
550 reg = <0x4000 0x4>,
551 <0x4010 0x4>,
552 <0x4014 0x4>;
564 ranges = <0 0x4000 0x1000>;
566 dsi1: encoder@0 {
568 reg = <0 0x200>,
569 <0x200 0x40>,
570 <0x300 0x40>;
579 #size-cells = <0>;
585 reg = <0x9000 0x4>,
586 <0x9010 0x4>,
587 <0x9014 0x4>;
599 ranges = <0 0x9000 0x1000>;
601 dsi2: encoder@0 {
603 reg = <0 0x200>,
604 <0x200 0x40>,
605 <0x300 0x40>;
614 #size-cells = <0>;
620 reg = <0x40000 0x4>,
621 <0x40010 0x4>;
633 ranges = <0 0x40000 0x40000>;
635 hdmi: encoder@0 {
637 reg = <0 0x200>,
638 <0x200 0x80>,
639 <0x300 0x80>,
640 <0x20000 0x19000>;
657 #address-cells = <0>;
658 #size-cells = <0>;
663 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
664 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
667 ti,tranxdone-status-mask = <0x80>;
669 ti,ldovbb-override-mask = <0x400>;
671 ti,ldovbb-vset-mask = <0x1F>;
679 1060000 0 0x0 0 0x02000000 0x01F00000
680 1250000 0 0x4 0 0x02000000 0x01F00000
687 #address-cells = <0>;
688 #size-cells = <0>;
693 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
694 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
697 ti,tranxdone-status-mask = <0x80000000>;
699 ti,ldovbb-override-mask = <0x400>;
701 ti,ldovbb-vset-mask = <0x1F>;
709 1025000 0 0x0 0 0x02000000 0x01F00000
710 1120000 0 0x4 0 0x02000000 0x01F00000
729 coefficients = <0 2000>;
738 reg = <0x300 0x100>;
739 #power-domain-cells = <0>;
744 reg = <0x400 0x100>;
746 #power-domain-cells = <0>;
751 reg = <0x500 0x100>;
752 #power-domain-cells = <0>;
757 reg = <0x600 0x100>;
758 #power-domain-cells = <0>;
763 reg = <0x700 0x100>;
765 #power-domain-cells = <0>;
770 reg = <0x1200 0x100>;
772 #power-domain-cells = <0>;
777 reg = <0x1300 0x100>;
778 #power-domain-cells = <0>;
783 reg = <0x1400 0x100>;
784 #power-domain-cells = <0>;
789 reg = <0x1500 0x100>;
790 #power-domain-cells = <0>;
795 reg = <0x1600 0x100>;
796 #power-domain-cells = <0>;
801 reg = <0x1700 0x100>;
802 #power-domain-cells = <0>;
807 reg = <0x1800 0x100>;
808 #power-domain-cells = <0>;
813 reg = <0x1a00 0x100>;
814 #power-domain-cells = <0>;
819 reg = <0x1c00 0x100>;
828 timer@0 {