Lines Matching +full:0 +full:x32000
1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
17 <0x00280000 0x4a280000 0x080000>, /* segment 5 */
18 <0x00300000 0x4a300000 0x080000>; /* segment 6 */
20 segment@0 { /* 0x4a000000 */
24 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
25 <0x00001000 0x00001000 0x001000>, /* ap 1 */
26 <0x00000800 0x00000800 0x000800>, /* ap 2 */
27 <0x00002000 0x00002000 0x001000>, /* ap 3 */
28 <0x00003000 0x00003000 0x001000>, /* ap 4 */
29 <0x00004000 0x00004000 0x001000>, /* ap 5 */
30 <0x00005000 0x00005000 0x001000>, /* ap 6 */
31 <0x00056000 0x00056000 0x001000>, /* ap 7 */
32 <0x00057000 0x00057000 0x001000>, /* ap 8 */
33 <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
34 <0x00058000 0x00058000 0x001000>, /* ap 10 */
35 <0x00062000 0x00062000 0x001000>, /* ap 11 */
36 <0x00063000 0x00063000 0x001000>, /* ap 12 */
37 <0x00008000 0x00008000 0x002000>, /* ap 21 */
38 <0x0000a000 0x0000a000 0x001000>, /* ap 22 */
39 <0x00066000 0x00066000 0x001000>, /* ap 23 */
40 <0x00067000 0x00067000 0x001000>, /* ap 24 */
41 <0x0005e000 0x0005e000 0x002000>, /* ap 69 */
42 <0x00060000 0x00060000 0x001000>, /* ap 70 */
43 <0x00064000 0x00064000 0x001000>, /* ap 71 */
44 <0x00065000 0x00065000 0x001000>, /* ap 72 */
45 <0x0005a000 0x0005a000 0x001000>, /* ap 77 */
46 <0x0005b000 0x0005b000 0x001000>, /* ap 78 */
47 <0x00070000 0x00070000 0x004000>, /* ap 79 */
48 <0x00074000 0x00074000 0x001000>, /* ap 80 */
49 <0x00075000 0x00075000 0x001000>, /* ap 81 */
50 <0x00076000 0x00076000 0x001000>, /* ap 82 */
51 <0x00020000 0x00020000 0x020000>, /* ap 109 */
52 <0x00040000 0x00040000 0x001000>, /* ap 110 */
53 <0x00059000 0x00059000 0x001000>; /* ap 111 */
55 target-module@2000 { /* 0x4a002000, ap 3 44.0 */
57 reg = <0x2000 0x4>;
61 ranges = <0x0 0x2000 0x1000>;
63 scm_core: scm@0 {
65 reg = <0x0 0x1000>;
68 ranges = <0 0 0x800>;
70 scm_conf: scm_conf@0 {
72 reg = <0x0 0x800>;
83 ranges = <0 0x800 0x800>;
88 reg = <0x40 0x01b6>;
90 #size-cells = <0>;
95 pinctrl-single,function-mask = <0x7fff>;
101 reg = <0x5a0 0xec>;
104 ranges = <0 0x5a0 0xec>;
108 reg = <0x60 0x4>;
120 target-module@4000 { /* 0x4a004000, ap 5 5c.0 */
122 reg = <0x4000 0x4>;
126 ranges = <0x0 0x4000 0x1000>;
128 cm_core_aon: cm_core_aon@0 {
131 reg = <0x0 0x2000>;
134 ranges = <0 0 0x1000>;
138 #size-cells = <0>;
146 target-module@8000 { /* 0x4a008000, ap 21 4c.0 */
148 reg = <0x8000 0x4>;
152 ranges = <0x0 0x8000 0x2000>;
154 cm_core: cm_core@0 {
156 reg = <0x0 0x2000>;
159 ranges = <0 0 0x2000>;
163 #size-cells = <0>;
171 target-module@20000 { /* 0x4a020000, ap 109 08.0 */
173 reg = <0x20000 0x4>,
174 <0x20010 0x4>;
186 clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>;
190 ranges = <0x0 0x20000 0x20000>;
192 usb3: omap_dwc3@0 {
194 reg = <0x0 0x10000>;
199 ranges = <0 0 0x20000>;
202 reg = <0x10000 0x10000>;
216 target-module@56000 { /* 0x4a056000, ap 7 02.0 */
218 reg = <0x56000 0x4>,
219 <0x5602c 0x4>,
220 <0x56028 0x4>;
234 clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>;
238 ranges = <0x0 0x56000 0x1000>;
240 sdma: dma-controller@0 {
242 reg = <0x0 0x1000>;
253 target-module@58000 { /* 0x4a058000, ap 10 06.0 */
258 ranges = <0x00000000 0x00058000 0x00001000>,
259 <0x00001000 0x00059000 0x00001000>,
260 <0x00002000 0x0005a000 0x00001000>,
261 <0x00003000 0x0005b000 0x00001000>;
264 target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */
269 ranges = <0x0 0x5e000 0x2000>;
272 target-module@62000 { /* 0x4a062000, ap 11 0e.0 */
274 reg = <0x62000 0x4>,
275 <0x62010 0x4>,
276 <0x62014 0x4>;
287 clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>;
291 ranges = <0x0 0x62000 0x1000>;
293 usbhstll: usbhstll@0 {
295 reg = <0x0 0x1000>;
300 target-module@64000 { /* 0x4a064000, ap 71 1e.0 */
302 reg = <0x64000 0x4>,
303 <0x64010 0x4>;
315 clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>;
319 ranges = <0x0 0x64000 0x1000>;
321 usbhshost: usbhshost@0 {
323 reg = <0x0 0x800>;
326 ranges = <0 0 0x1000>;
336 reg = <0x800 0x400>;
343 reg = <0xc00 0x400>;
349 target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
351 reg = <0x66000 0x4>,
352 <0x66010 0x4>,
353 <0x66014 0x4>;
363 clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
369 ranges = <0x0 0x66000 0x1000>;
371 mmu_dsp: mmu@0 {
373 reg = <0x0 0x100>;
375 #iommu-cells = <0>;
379 target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
384 ranges = <0x0 0x70000 0x4000>;
387 target-module@75000 { /* 0x4a075000, ap 81 32.0 */
392 ranges = <0x0 0x75000 0x1000>;
396 segment@80000 { /* 0x4a080000 */
400 ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
401 <0x0005a000 0x000da000 0x001000>, /* ap 14 */
402 <0x0005b000 0x000db000 0x001000>, /* ap 15 */
403 <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
404 <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
405 <0x0005e000 0x000de000 0x001000>, /* ap 18 */
406 <0x00060000 0x000e0000 0x001000>, /* ap 19 */
407 <0x00061000 0x000e1000 0x001000>, /* ap 20 */
408 <0x00074000 0x000f4000 0x001000>, /* ap 25 */
409 <0x00075000 0x000f5000 0x001000>, /* ap 26 */
410 <0x00076000 0x000f6000 0x001000>, /* ap 27 */
411 <0x00077000 0x000f7000 0x001000>, /* ap 28 */
412 <0x00036000 0x000b6000 0x001000>, /* ap 65 */
413 <0x00037000 0x000b7000 0x001000>, /* ap 66 */
414 <0x0004d000 0x000cd000 0x001000>, /* ap 67 */
415 <0x0004e000 0x000ce000 0x001000>, /* ap 68 */
416 <0x00000000 0x00080000 0x004000>, /* ap 83 */
417 <0x00004000 0x00084000 0x001000>, /* ap 84 */
418 <0x00005000 0x00085000 0x001000>, /* ap 85 */
419 <0x00006000 0x00086000 0x001000>, /* ap 86 */
420 <0x00007000 0x00087000 0x001000>, /* ap 87 */
421 <0x00008000 0x00088000 0x001000>, /* ap 88 */
422 <0x00010000 0x00090000 0x004000>, /* ap 89 */
423 <0x00014000 0x00094000 0x001000>, /* ap 90 */
424 <0x00015000 0x00095000 0x001000>, /* ap 91 */
425 <0x00016000 0x00096000 0x001000>, /* ap 92 */
426 <0x00017000 0x00097000 0x001000>, /* ap 93 */
427 <0x00018000 0x00098000 0x001000>, /* ap 94 */
428 <0x00020000 0x000a0000 0x004000>, /* ap 95 */
429 <0x00024000 0x000a4000 0x001000>, /* ap 96 */
430 <0x00025000 0x000a5000 0x001000>, /* ap 97 */
431 <0x00026000 0x000a6000 0x001000>, /* ap 98 */
432 <0x00027000 0x000a7000 0x001000>, /* ap 99 */
433 <0x00028000 0x000a8000 0x001000>; /* ap 100 */
435 target-module@0 { /* 0x4a080000, ap 83 28.0 */
437 reg = <0x0 0x4>,
438 <0x10 0x4>,
439 <0x14 0x4>;
448 clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>;
452 ranges = <0x00000000 0x00000000 0x00004000>,
453 <0x00004000 0x00004000 0x00001000>,
454 <0x00005000 0x00005000 0x00001000>,
455 <0x00006000 0x00006000 0x00001000>,
456 <0x00007000 0x00007000 0x00001000>;
458 ocp2scp@0 {
462 reg = <0 0x20>;
467 reg = <0x4000 0x7c>;
468 syscon-phy-power = <&scm_conf 0x300>;
472 #phy-cells = <0>;
477 reg = <0x4400 0x80>,
478 <0x4800 0x64>,
479 <0x4c00 0x40>;
481 syscon-phy-power = <&scm_conf 0x370>;
488 #phy-cells = <0>;
492 target-module@10000 { /* 0x4a090000, ap 89 36.0 */
494 reg = <0x10000 0x4>,
495 <0x10010 0x4>,
496 <0x10014 0x4>;
505 clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>;
509 ranges = <0x00000000 0x00010000 0x00004000>,
510 <0x00004000 0x00014000 0x00001000>,
511 <0x00005000 0x00015000 0x00001000>,
512 <0x00006000 0x00016000 0x00001000>,
513 <0x00007000 0x00017000 0x00001000>;
515 ocp2scp@0 {
519 reg = <0x0 0x20>;
524 reg = <0x6000 0x80>, /* phy_rx */
525 <0x6400 0x64>, /* phy_tx */
526 <0x6800 0x40>; /* pll_ctrl */
528 syscon-phy-power = <&scm_conf 0x374>;
532 #phy-cells = <0>;
536 target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */
541 ranges = <0x00000000 0x00020000 0x00004000>,
542 <0x00004000 0x00024000 0x00001000>,
543 <0x00005000 0x00025000 0x00001000>,
544 <0x00006000 0x00026000 0x00001000>,
545 <0x00007000 0x00027000 0x00001000>;
548 target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */
553 ranges = <0x0 0x36000 0x1000>;
556 target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */
561 ranges = <0x0 0x4d000 0x1000>;
564 target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */
569 ranges = <0x0 0x59000 0x1000>;
572 target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */
577 ranges = <0x0 0x5b000 0x1000>;
580 target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */
585 ranges = <0x0 0x5d000 0x1000>;
588 target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */
593 ranges = <0x0 0x60000 0x1000>;
596 target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */
598 reg = <0x74000 0x4>,
599 <0x74010 0x4>;
606 clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>;
610 ranges = <0x0 0x74000 0x1000>;
612 mailbox: mailbox@0 {
614 reg = <0x0 0x200>;
620 ti,mbox-tx = <0 0 0>;
621 ti,mbox-rx = <1 0 0>;
624 ti,mbox-tx = <3 0 0>;
625 ti,mbox-rx = <2 0 0>;
630 target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */
632 reg = <0x76000 0x4>,
633 <0x76010 0x4>,
634 <0x76014 0x4>;
645 clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>;
649 ranges = <0x0 0x76000 0x1000>;
651 hwspinlock: spinlock@0 {
653 reg = <0x0 0x1000>;
659 segment@100000 { /* 0x4a100000 */
663 ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */
664 <0x00003000 0x00103000 0x001000>, /* ap 60 */
665 <0x00008000 0x00108000 0x001000>, /* ap 61 */
666 <0x00009000 0x00109000 0x001000>, /* ap 62 */
667 <0x0000a000 0x0010a000 0x001000>, /* ap 63 */
668 <0x0000b000 0x0010b000 0x001000>, /* ap 64 */
669 <0x00040000 0x00140000 0x010000>, /* ap 101 */
670 <0x00050000 0x00150000 0x001000>; /* ap 102 */
672 target-module@2000 { /* 0x4a102000, ap 59 2c.0 */
677 ranges = <0x0 0x2000 0x1000>;
680 target-module@8000 { /* 0x4a108000, ap 61 26.0 */
685 ranges = <0x0 0x8000 0x1000>;
688 target-module@a000 { /* 0x4a10a000, ap 63 22.0 */
693 ranges = <0x0 0xa000 0x1000>;
696 target-module@40000 { /* 0x4a140000, ap 101 16.0 */
698 reg = <0x400fc 4>,
699 <0x41100 4>;
709 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 0>;
713 ranges = <0x0 0x40000 0x10000>;
715 sata: sata@0 {
717 reg = <0 0x1100>, <0x1100 0x8>;
722 ports-implemented = <0x1>;
727 segment@180000 { /* 0x4a180000 */
733 segment@200000 { /* 0x4a200000 */
737 ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */
738 <0x0001f000 0x0021f000 0x001000>, /* ap 30 */
739 <0x0000a000 0x0020a000 0x001000>, /* ap 31 */
740 <0x0000b000 0x0020b000 0x001000>, /* ap 32 */
741 <0x00006000 0x00206000 0x001000>, /* ap 33 */
742 <0x00007000 0x00207000 0x001000>, /* ap 34 */
743 <0x00004000 0x00204000 0x001000>, /* ap 35 */
744 <0x00005000 0x00205000 0x001000>, /* ap 36 */
745 <0x00012000 0x00212000 0x001000>, /* ap 37 */
746 <0x00013000 0x00213000 0x001000>, /* ap 38 */
747 <0x0000c000 0x0020c000 0x001000>, /* ap 39 */
748 <0x0000d000 0x0020d000 0x001000>, /* ap 40 */
749 <0x00010000 0x00210000 0x001000>, /* ap 41 */
750 <0x00011000 0x00211000 0x001000>, /* ap 42 */
751 <0x00016000 0x00216000 0x001000>, /* ap 43 */
752 <0x00017000 0x00217000 0x001000>, /* ap 44 */
753 <0x00014000 0x00214000 0x001000>, /* ap 45 */
754 <0x00015000 0x00215000 0x001000>, /* ap 46 */
755 <0x00018000 0x00218000 0x001000>, /* ap 47 */
756 <0x00019000 0x00219000 0x001000>, /* ap 48 */
757 <0x00020000 0x00220000 0x001000>, /* ap 49 */
758 <0x00021000 0x00221000 0x001000>, /* ap 50 */
759 <0x00026000 0x00226000 0x001000>, /* ap 51 */
760 <0x00027000 0x00227000 0x001000>, /* ap 52 */
761 <0x00028000 0x00228000 0x001000>, /* ap 53 */
762 <0x00029000 0x00229000 0x001000>, /* ap 54 */
763 <0x0002a000 0x0022a000 0x001000>, /* ap 55 */
764 <0x0002b000 0x0022b000 0x001000>, /* ap 56 */
765 <0x0001c000 0x0021c000 0x001000>, /* ap 57 */
766 <0x0001d000 0x0021d000 0x001000>, /* ap 58 */
767 <0x0001a000 0x0021a000 0x001000>, /* ap 73 */
768 <0x0001b000 0x0021b000 0x001000>, /* ap 74 */
769 <0x00024000 0x00224000 0x001000>, /* ap 75 */
770 <0x00025000 0x00225000 0x001000>, /* ap 76 */
771 <0x00002000 0x00202000 0x001000>, /* ap 103 */
772 <0x00003000 0x00203000 0x001000>, /* ap 104 */
773 <0x00008000 0x00208000 0x001000>, /* ap 105 */
774 <0x00009000 0x00209000 0x001000>, /* ap 106 */
775 <0x00022000 0x00222000 0x001000>, /* ap 107 */
776 <0x00023000 0x00223000 0x001000>; /* ap 108 */
778 target-module@2000 { /* 0x4a202000, ap 103 3c.0 */
783 ranges = <0x0 0x2000 0x1000>;
786 target-module@4000 { /* 0x4a204000, ap 35 46.0 */
791 ranges = <0x0 0x4000 0x1000>;
794 target-module@6000 { /* 0x4a206000, ap 33 4e.0 */
799 ranges = <0x0 0x6000 0x1000>;
802 target-module@8000 { /* 0x4a208000, ap 105 34.0 */
807 ranges = <0x0 0x8000 0x1000>;
810 target-module@a000 { /* 0x4a20a000, ap 31 30.0 */
815 ranges = <0x0 0xa000 0x1000>;
818 target-module@c000 { /* 0x4a20c000, ap 39 14.0 */
823 ranges = <0x0 0xc000 0x1000>;
826 target-module@10000 { /* 0x4a210000, ap 41 56.0 */
831 ranges = <0x0 0x10000 0x1000>;
834 target-module@12000 { /* 0x4a212000, ap 37 52.0 */
839 ranges = <0x0 0x12000 0x1000>;
842 target-module@14000 { /* 0x4a214000, ap 45 1c.0 */
847 ranges = <0x0 0x14000 0x1000>;
850 target-module@16000 { /* 0x4a216000, ap 43 42.0 */
855 ranges = <0x0 0x16000 0x1000>;
858 target-module@18000 { /* 0x4a218000, ap 47 1a.0 */
863 ranges = <0x0 0x18000 0x1000>;
866 target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */
871 ranges = <0x0 0x1a000 0x1000>;
874 target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */
879 ranges = <0x0 0x1c000 0x1000>;
882 target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */
887 ranges = <0x0 0x1e000 0x1000>;
890 target-module@20000 { /* 0x4a220000, ap 49 4a.0 */
895 ranges = <0x0 0x20000 0x1000>;
898 target-module@22000 { /* 0x4a222000, ap 107 3a.0 */
903 ranges = <0x0 0x22000 0x1000>;
906 target-module@24000 { /* 0x4a224000, ap 75 48.0 */
911 ranges = <0x0 0x24000 0x1000>;
914 target-module@26000 { /* 0x4a226000, ap 51 24.0 */
919 ranges = <0x0 0x26000 0x1000>;
922 target-module@28000 { /* 0x4a228000, ap 53 38.0 */
927 ranges = <0x0 0x28000 0x1000>;
930 target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */
935 ranges = <0x0 0x2a000 0x1000>;
939 segment@280000 { /* 0x4a280000 */
945 segment@300000 { /* 0x4a300000 */
952 &l4_per { /* 0x48000000 */
955 clocks = <&l4per_clkctrl OMAP5_L4_PER_CLKCTRL 0>;
957 reg = <0x48000000 0x800>,
958 <0x48000800 0x800>,
959 <0x48001000 0x400>,
960 <0x48001400 0x400>,
961 <0x48001800 0x400>,
962 <0x48001c00 0x400>;
966 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
967 <0x00200000 0x48200000 0x200000>; /* segment 1 */
969 segment@0 { /* 0x48000000 */
973 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
974 <0x00001000 0x00001000 0x000400>, /* ap 1 */
975 <0x00000800 0x00000800 0x000800>, /* ap 2 */
976 <0x00020000 0x00020000 0x001000>, /* ap 3 */
977 <0x00021000 0x00021000 0x001000>, /* ap 4 */
978 <0x00032000 0x00032000 0x001000>, /* ap 5 */
979 <0x00033000 0x00033000 0x001000>, /* ap 6 */
980 <0x00034000 0x00034000 0x001000>, /* ap 7 */
981 <0x00035000 0x00035000 0x001000>, /* ap 8 */
982 <0x00036000 0x00036000 0x001000>, /* ap 9 */
983 <0x00037000 0x00037000 0x001000>, /* ap 10 */
984 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
985 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
986 <0x00055000 0x00055000 0x001000>, /* ap 13 */
987 <0x00056000 0x00056000 0x001000>, /* ap 14 */
988 <0x00057000 0x00057000 0x001000>, /* ap 15 */
989 <0x00058000 0x00058000 0x001000>, /* ap 16 */
990 <0x00059000 0x00059000 0x001000>, /* ap 17 */
991 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
992 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
993 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
994 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
995 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
996 <0x00060000 0x00060000 0x001000>, /* ap 23 */
997 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
998 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
999 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
1000 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
1001 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
1002 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
1003 <0x00070000 0x00070000 0x001000>, /* ap 30 */
1004 <0x00071000 0x00071000 0x001000>, /* ap 31 */
1005 <0x00072000 0x00072000 0x001000>, /* ap 32 */
1006 <0x00073000 0x00073000 0x001000>, /* ap 33 */
1007 <0x00061000 0x00061000 0x001000>, /* ap 34 */
1008 <0x00053000 0x00053000 0x001000>, /* ap 35 */
1009 <0x00054000 0x00054000 0x001000>, /* ap 36 */
1010 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
1011 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
1012 <0x00078000 0x00078000 0x001000>, /* ap 39 */
1013 <0x00079000 0x00079000 0x001000>, /* ap 40 */
1014 <0x00086000 0x00086000 0x001000>, /* ap 41 */
1015 <0x00087000 0x00087000 0x001000>, /* ap 42 */
1016 <0x00088000 0x00088000 0x001000>, /* ap 43 */
1017 <0x00089000 0x00089000 0x001000>, /* ap 44 */
1018 <0x00051000 0x00051000 0x001000>, /* ap 45 */
1019 <0x00052000 0x00052000 0x001000>, /* ap 46 */
1020 <0x00098000 0x00098000 0x001000>, /* ap 47 */
1021 <0x00099000 0x00099000 0x001000>, /* ap 48 */
1022 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
1023 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
1024 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
1025 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
1026 <0x00068000 0x00068000 0x001000>, /* ap 53 */
1027 <0x00069000 0x00069000 0x001000>, /* ap 54 */
1028 <0x00090000 0x00090000 0x002000>, /* ap 55 */
1029 <0x00092000 0x00092000 0x001000>, /* ap 56 */
1030 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
1031 <0x000a5000 0x000a5000 0x001000>,
1032 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
1033 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
1034 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
1035 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
1036 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
1037 <0x00066000 0x00066000 0x001000>, /* ap 63 */
1038 <0x00067000 0x00067000 0x001000>, /* ap 64 */
1039 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
1040 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
1041 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
1042 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
1043 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
1044 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
1045 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
1046 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
1047 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
1048 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
1049 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
1050 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
1051 <0x00001400 0x00001400 0x000400>, /* ap 77 */
1052 <0x00001800 0x00001800 0x000400>, /* ap 78 */
1053 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
1054 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
1055 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
1056 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
1057 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
1058 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
1060 target-module@20000 { /* 0x48020000, ap 3 04.0 */
1062 reg = <0x20050 0x4>,
1063 <0x20054 0x4>,
1064 <0x20058 0x4>;
1075 clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>;
1079 ranges = <0x0 0x20000 0x1000>;
1081 uart3: serial@0 {
1083 reg = <0x0 0x100>;
1089 target-module@32000 { /* 0x48032000, ap 5 3e.0 */
1091 reg = <0x32000 0x4>,
1092 <0x32010 0x4>;
1101 clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>;
1105 ranges = <0x0 0x32000 0x1000>;
1107 timer2: timer@0 {
1109 reg = <0x0 0x80>;
1117 target-module@34000 { /* 0x48034000, ap 7 46.0 */
1119 reg = <0x34000 0x4>,
1120 <0x34010 0x4>;
1129 clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>;
1133 ranges = <0x0 0x34000 0x1000>;
1135 timer3: timer@0 {
1137 reg = <0x0 0x80>;
1145 target-module@36000 { /* 0x48036000, ap 9 4e.0 */
1147 reg = <0x36000 0x4>,
1148 <0x36010 0x4>;
1157 clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>;
1161 ranges = <0x0 0x36000 0x1000>;
1163 timer4: timer@0 {
1165 reg = <0x0 0x80>;
1173 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
1175 reg = <0x3e000 0x4>,
1176 <0x3e010 0x4>;
1185 clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>;
1189 ranges = <0x0 0x3e000 0x1000>;
1191 timer9: timer@0 {
1193 reg = <0x0 0x80>;
1202 target-module@51000 { /* 0x48051000, ap 45 2e.0 */
1204 reg = <0x51000 0x4>,
1205 <0x51010 0x4>,
1206 <0x51114 0x4>;
1217 clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>,
1222 ranges = <0x0 0x51000 0x1000>;
1224 gpio7: gpio@0 {
1226 reg = <0x0 0x200>;
1235 target-module@53000 { /* 0x48053000, ap 35 36.0 */
1237 reg = <0x53000 0x4>,
1238 <0x53010 0x4>,
1239 <0x53114 0x4>;
1250 clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>,
1255 ranges = <0x0 0x53000 0x1000>;
1257 gpio8: gpio@0 {
1259 reg = <0x0 0x200>;
1268 target-module@55000 { /* 0x48055000, ap 13 0e.0 */
1270 reg = <0x55000 0x4>,
1271 <0x55010 0x4>,
1272 <0x55114 0x4>;
1283 clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>,
1288 ranges = <0x0 0x55000 0x1000>;
1290 gpio2: gpio@0 {
1292 reg = <0x0 0x200>;
1301 target-module@57000 { /* 0x48057000, ap 15 06.0 */
1303 reg = <0x57000 0x4>,
1304 <0x57010 0x4>,
1305 <0x57114 0x4>;
1316 clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>,
1321 ranges = <0x0 0x57000 0x1000>;
1323 gpio3: gpio@0 {
1325 reg = <0x0 0x200>;
1334 target-module@59000 { /* 0x48059000, ap 17 16.0 */
1336 reg = <0x59000 0x4>,
1337 <0x59010 0x4>,
1338 <0x59114 0x4>;
1349 clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>,
1354 ranges = <0x0 0x59000 0x1000>;
1356 gpio4: gpio@0 {
1358 reg = <0x0 0x200>;
1367 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
1369 reg = <0x5b000 0x4>,
1370 <0x5b010 0x4>,
1371 <0x5b114 0x4>;
1382 clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>,
1387 ranges = <0x0 0x5b000 0x1000>;
1389 gpio5: gpio@0 {
1391 reg = <0x0 0x200>;
1400 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
1402 reg = <0x5d000 0x4>,
1403 <0x5d010 0x4>,
1404 <0x5d114 0x4>;
1415 clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>,
1420 ranges = <0x0 0x5d000 0x1000>;
1422 gpio6: gpio@0 {
1424 reg = <0x0 0x200>;
1433 target-module@60000 { /* 0x48060000, ap 23 24.0 */
1435 reg = <0x60000 0x8>,
1436 <0x60010 0x8>,
1437 <0x60090 0x8>;
1449 clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>;
1453 ranges = <0x0 0x60000 0x1000>;
1455 i2c3: i2c@0 {
1457 reg = <0x0 0x100>;
1460 #size-cells = <0>;
1464 target-module@66000 { /* 0x48066000, ap 63 4c.0 */
1466 reg = <0x66050 0x4>,
1467 <0x66054 0x4>,
1468 <0x66058 0x4>;
1479 clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>;
1483 ranges = <0x0 0x66000 0x1000>;
1485 uart5: serial@0 {
1487 reg = <0x0 0x100>;
1493 target-module@68000 { /* 0x48068000, ap 53 54.0 */
1495 reg = <0x68050 0x4>,
1496 <0x68054 0x4>,
1497 <0x68058 0x4>;
1508 clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>;
1512 ranges = <0x0 0x68000 0x1000>;
1514 uart6: serial@0 {
1516 reg = <0x0 0x100>;
1522 target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */
1524 reg = <0x6a050 0x4>,
1525 <0x6a054 0x4>,
1526 <0x6a058 0x4>;
1537 clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>;
1541 ranges = <0x0 0x6a000 0x1000>;
1543 uart1: serial@0 {
1545 reg = <0x0 0x100>;
1551 target-module@6c000 { /* 0x4806c000, ap 26 22.0 */
1553 reg = <0x6c050 0x4>,
1554 <0x6c054 0x4>,
1555 <0x6c058 0x4>;
1566 clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>;
1570 ranges = <0x0 0x6c000 0x1000>;
1572 uart2: serial@0 {
1574 reg = <0x0 0x100>;
1580 target-module@6e000 { /* 0x4806e000, ap 28 44.1 */
1582 reg = <0x6e050 0x4>,
1583 <0x6e054 0x4>,
1584 <0x6e058 0x4>;
1595 clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>;
1599 ranges = <0x0 0x6e000 0x1000>;
1601 uart4: serial@0 {
1603 reg = <0x0 0x100>;
1609 target-module@70000 { /* 0x48070000, ap 30 14.0 */
1611 reg = <0x70000 0x8>,
1612 <0x70010 0x8>,
1613 <0x70090 0x8>;
1625 clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>;
1629 ranges = <0x0 0x70000 0x1000>;
1631 i2c1: i2c@0 {
1633 reg = <0x0 0x100>;
1636 #size-cells = <0>;
1640 target-module@72000 { /* 0x48072000, ap 32 1c.0 */
1642 reg = <0x72000 0x8>,
1643 <0x72010 0x8>,
1644 <0x72090 0x8>;
1656 clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>;
1660 ranges = <0x0 0x72000 0x1000>;
1662 i2c2: i2c@0 {
1664 reg = <0x0 0x100>;
1667 #size-cells = <0>;
1671 target-module@78000 { /* 0x48078000, ap 39 12.0 */
1676 ranges = <0x0 0x78000 0x1000>;
1679 target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */
1681 reg = <0x7a000 0x8>,
1682 <0x7a010 0x8>,
1683 <0x7a090 0x8>;
1695 clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>;
1699 ranges = <0x0 0x7a000 0x1000>;
1701 i2c4: i2c@0 {
1703 reg = <0x0 0x100>;
1706 #size-cells = <0>;
1710 target-module@7c000 { /* 0x4807c000, ap 83 34.0 */
1712 reg = <0x7c000 0x8>,
1713 <0x7c010 0x8>,
1714 <0x7c090 0x8>;
1726 clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>;
1730 ranges = <0x0 0x7c000 0x1000>;
1732 i2c5: i2c@0 {
1734 reg = <0x0 0x100>;
1737 #size-cells = <0>;
1741 target-module@86000 { /* 0x48086000, ap 41 5e.0 */
1743 reg = <0x86000 0x4>,
1744 <0x86010 0x4>;
1753 clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>;
1757 ranges = <0x0 0x86000 0x1000>;
1759 timer10: timer@0 {
1761 reg = <0x0 0x80>;
1770 target-module@88000 { /* 0x48088000, ap 43 66.0 */
1772 reg = <0x88000 0x4>,
1773 <0x88010 0x4>;
1782 clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>;
1786 ranges = <0x0 0x88000 0x1000>;
1788 timer11: timer@0 {
1790 reg = <0x0 0x80>;
1799 rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */
1801 reg = <0x91fe0 0x4>,
1802 <0x91fe4 0x4>;
1808 clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>;
1812 ranges = <0x0 0x90000 0x2000>;
1814 rng: rng@0 {
1816 reg = <0x0 0x2000>;
1821 target-module@98000 { /* 0x48098000, ap 47 08.0 */
1823 reg = <0x98000 0x4>,
1824 <0x98010 0x4>;
1833 clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>;
1837 ranges = <0x0 0x98000 0x1000>;
1839 mcspi1: spi@0 {
1841 reg = <0x0 0x200>;
1844 #size-cells = <0>;
1859 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
1861 reg = <0x9a000 0x4>,
1862 <0x9a010 0x4>;
1871 clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>;
1875 ranges = <0x0 0x9a000 0x1000>;
1877 mcspi2: spi@0 {
1879 reg = <0x0 0x200>;
1882 #size-cells = <0>;
1892 target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */
1894 reg = <0x9c000 0x4>,
1895 <0x9c010 0x4>;
1908 clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>;
1912 ranges = <0x0 0x9c000 0x1000>;
1914 mmc1: mmc@0 {
1916 reg = <0x0 0x400>;
1926 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
1931 ranges = <0x0 0xa2000 0x1000>;
1934 target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */
1939 ranges = <0x00000000 0x000a4000 0x00001000>,
1940 <0x00001000 0x000a5000 0x00001000>;
1943 des_target: target-module@a5000 { /* 0x480a5000 */
1945 reg = <0xa5030 0x4>,
1946 <0xa5034 0x4>,
1947 <0xa5038 0x4>;
1957 clocks = <&l4sec_clkctrl OMAP5_DES3DES_CLKCTRL 0>;
1961 ranges = <0 0xa5000 0x00001000>;
1964 des: des@0 {
1966 reg = <0 0xa0>;
1973 target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */
1978 ranges = <0x0 0xa8000 0x4000>;
1981 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
1983 reg = <0xad000 0x4>,
1984 <0xad010 0x4>;
1997 clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>;
2001 ranges = <0x0 0xad000 0x1000>;
2003 mmc3: mmc@0 {
2005 reg = <0x0 0x400>;
2013 target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */
2018 ranges = <0x0 0xb2000 0x1000>;
2021 target-module@b4000 { /* 0x480b4000, ap 65 42.0 */
2023 reg = <0xb4000 0x4>,
2024 <0xb4010 0x4>;
2037 clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>;
2041 ranges = <0x0 0xb4000 0x1000>;
2043 mmc2: mmc@0 {
2045 reg = <0x0 0x400>;
2053 target-module@b8000 { /* 0x480b8000, ap 67 32.0 */
2055 reg = <0xb8000 0x4>,
2056 <0xb8010 0x4>;
2065 clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>;
2069 ranges = <0x0 0xb8000 0x1000>;
2071 mcspi3: spi@0 {
2073 reg = <0x0 0x200>;
2076 #size-cells = <0>;
2083 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
2085 reg = <0xba000 0x4>,
2086 <0xba010 0x4>;
2095 clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>;
2099 ranges = <0x0 0xba000 0x1000>;
2101 mcspi4: spi@0 {
2103 reg = <0x0 0x200>;
2106 #size-cells = <0>;
2113 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
2115 reg = <0xd1000 0x4>,
2116 <0xd1010 0x4>;
2129 clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>;
2133 ranges = <0x0 0xd1000 0x1000>;
2135 mmc4: mmc@0 {
2137 reg = <0x0 0x400>;
2145 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
2147 reg = <0xd5000 0x4>,
2148 <0xd5010 0x4>;
2161 clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>;
2165 ranges = <0x0 0xd5000 0x1000>;
2167 mmc5: mmc@0 {
2169 reg = <0x0 0x400>;
2178 segment@200000 { /* 0x48200000 */
2185 &l4_wkup { /* 0x4ae00000 */
2188 clocks = <&wkupaon_clkctrl OMAP5_L4_WKUP_CLKCTRL 0>;
2190 reg = <0x4ae00000 0x800>,
2191 <0x4ae00800 0x800>,
2192 <0x4ae01000 0x1000>;
2196 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
2197 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
2198 <0x00020000 0x4ae20000 0x010000>; /* segment 2 */
2200 segment@0 { /* 0x4ae00000 */
2204 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
2205 <0x00001000 0x00001000 0x001000>, /* ap 1 */
2206 <0x00000800 0x00000800 0x000800>, /* ap 2 */
2207 <0x00006000 0x00006000 0x002000>, /* ap 3 */
2208 <0x00008000 0x00008000 0x001000>, /* ap 4 */
2209 <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
2210 <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
2211 <0x00004000 0x00004000 0x001000>, /* ap 17 */
2212 <0x00005000 0x00005000 0x001000>, /* ap 18 */
2213 <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
2214 <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
2216 target-module@4000 { /* 0x4ae04000, ap 17 20.0 */
2218 reg = <0x4000 0x4>,
2219 <0x4010 0x4>;
2224 clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>;
2228 ranges = <0x0 0x4000 0x1000>;
2230 counter32k: counter@0 {
2232 reg = <0x0 0x40>;
2236 target-module@6000 { /* 0x4ae06000, ap 3 08.0 */
2238 reg = <0x6000 0x4>;
2242 ranges = <0x0 0x6000 0x2000>;
2244 prm: prm@0 {
2246 reg = <0x0 0x2000>;
2250 ranges = <0 0 0x2000>;
2254 #size-cells = <0>;
2262 target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */
2264 reg = <0xa000 0x4>;
2268 ranges = <0x0 0xa000 0x1000>;
2270 scrm: scrm@0 {
2272 reg = <0x0 0x1000>;
2276 #size-cells = <0>;
2284 target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */
2286 reg = <0xc000 0x4>;
2290 ranges = <0x0 0xc000 0x1000>;
2295 reg = <0x840 0x003c>;
2297 #size-cells = <0>;
2302 pinctrl-single,function-mask = <0x7fff>;
2308 reg = <0xda0 0x60>;
2311 ranges = <0 0 0x60>;
2313 scm_wkup_pad_conf: scm_conf@0 {
2315 reg = <0x0 0x60>;
2318 ranges = <0 0x0 0x60>;
2320 scm_wkup_pad_conf_clocks: clocks@0 {
2322 #size-cells = <0>;
2329 segment@10000 { /* 0x4ae10000 */
2333 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
2334 <0x00001000 0x00011000 0x001000>, /* ap 6 */
2335 <0x00004000 0x00014000 0x001000>, /* ap 7 */
2336 <0x00005000 0x00015000 0x001000>, /* ap 8 */
2337 <0x00008000 0x00018000 0x001000>, /* ap 9 */
2338 <0x00009000 0x00019000 0x001000>, /* ap 10 */
2339 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
2340 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
2342 target-module@0 { /* 0x4ae10000, ap 5 10.0 */
2344 reg = <0x0 0x4>,
2345 <0x10 0x4>,
2346 <0x114 0x4>;
2357 clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>,
2362 ranges = <0x0 0x0 0x1000>;
2364 gpio1: gpio@0 {
2366 reg = <0x0 0x200>;
2376 target-module@4000 { /* 0x4ae14000, ap 7 14.0 */
2378 reg = <0x4000 0x4>,
2379 <0x4010 0x4>,
2380 <0x4014 0x4>;
2390 clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>;
2394 ranges = <0x0 0x4000 0x1000>;
2396 wdt2: wdt@0 {
2398 reg = <0x0 0x80>;
2403 timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
2405 reg = <0x8000 0x4>,
2406 <0x8010 0x4>;
2415 clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>;
2419 ranges = <0x0 0x8000 0x1000>;
2421 timer1: timer@0 {
2423 reg = <0x0 0x80>;
2432 target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */
2434 reg = <0xc000 0x4>,
2435 <0xc010 0x4>;
2443 clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>;
2447 ranges = <0x0 0xc000 0x1000>;
2449 keypad: keypad@0 {
2451 reg = <0x0 0x400>;
2456 segment@20000 { /* 0x4ae20000 */
2460 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
2461 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
2462 <0x00000000 0x00020000 0x001000>, /* ap 21 */
2463 <0x00001000 0x00021000 0x001000>, /* ap 22 */
2464 <0x00002000 0x00022000 0x001000>, /* ap 23 */
2465 <0x00003000 0x00023000 0x001000>, /* ap 24 */
2466 <0x00007000 0x00027000 0x000400>, /* ap 25 */
2467 <0x00008000 0x00028000 0x000800>, /* ap 26 */
2468 <0x00009000 0x00029000 0x000100>, /* ap 27 */
2469 <0x00008800 0x00028800 0x000200>, /* ap 28 */
2470 <0x00008a00 0x00028a00 0x000100>; /* ap 29 */
2472 target-module@0 { /* 0x4ae20000, ap 21 04.0 */
2477 ranges = <0x0 0x0 0x1000>;
2480 target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */
2485 ranges = <0x0 0x2000 0x1000>;
2488 target-module@6000 { /* 0x4ae26000, ap 13 24.0 */
2493 ranges = <0x00000000 0x00006000 0x00001000>,
2494 <0x00001000 0x00007000 0x00000400>,
2495 <0x00002000 0x00008000 0x00000800>,
2496 <0x00002800 0x00008800 0x00000200>,
2497 <0x00002a00 0x00008a00 0x00000100>,
2498 <0x00003000 0x00009000 0x00000100>;