Lines Matching +full:0 +full:x00001400
2 &l4_cfg { /* 0x4a000000 */
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>;
13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
18 <0x00280000 0x4a280000 0x080000>, /* segment 5 */
19 <0x00300000 0x4a300000 0x080000>; /* segment 6 */
21 segment@0 { /* 0x4a000000 */
25 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
26 <0x00001000 0x00001000 0x001000>, /* ap 1 */
27 <0x00000800 0x00000800 0x000800>, /* ap 2 */
28 <0x00002000 0x00002000 0x001000>, /* ap 3 */
29 <0x00003000 0x00003000 0x001000>, /* ap 4 */
30 <0x00004000 0x00004000 0x001000>, /* ap 5 */
31 <0x00005000 0x00005000 0x001000>, /* ap 6 */
32 <0x00056000 0x00056000 0x001000>, /* ap 7 */
33 <0x00057000 0x00057000 0x001000>, /* ap 8 */
34 <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
35 <0x00058000 0x00058000 0x004000>, /* ap 10 */
36 <0x00062000 0x00062000 0x001000>, /* ap 11 */
37 <0x00063000 0x00063000 0x001000>, /* ap 12 */
38 <0x00008000 0x00008000 0x002000>, /* ap 23 */
39 <0x0000a000 0x0000a000 0x001000>, /* ap 24 */
40 <0x00066000 0x00066000 0x001000>, /* ap 25 */
41 <0x00067000 0x00067000 0x001000>, /* ap 26 */
42 <0x0005e000 0x0005e000 0x002000>, /* ap 80 */
43 <0x00060000 0x00060000 0x001000>, /* ap 81 */
44 <0x00064000 0x00064000 0x001000>, /* ap 86 */
45 <0x00065000 0x00065000 0x001000>; /* ap 87 */
47 target-module@2000 { /* 0x4a002000, ap 3 06.0 */
49 reg = <0x2000 0x4>,
50 <0x2010 0x4>;
59 ranges = <0x0 0x2000 0x1000>;
61 omap4_scm_core: scm@0 {
63 reg = <0x0 0x1000>;
66 ranges = <0 0 0x1000>;
68 scm_conf: scm_conf@0 {
70 reg = <0x0 0x800>;
77 reg = <0x300 0x4>;
83 reg = <0x33c 0x4>;
89 target-module@4000 { /* 0x4a004000, ap 5 02.0 */
91 reg = <0x4000 0x4>;
95 ranges = <0x0 0x4000 0x1000>;
97 cm1: cm1@0 {
99 reg = <0x0 0x2000>;
102 ranges = <0 0 0x2000>;
106 #size-cells = <0>;
114 target-module@8000 { /* 0x4a008000, ap 23 32.0 */
116 reg = <0x8000 0x4>;
120 ranges = <0x0 0x8000 0x2000>;
122 cm2: cm2@0 {
124 reg = <0x0 0x2000>;
127 ranges = <0 0 0x2000>;
131 #size-cells = <0>;
139 target-module@56000 { /* 0x4a056000, ap 7 0a.0 */
141 reg = <0x56000 0x4>,
142 <0x5602c 0x4>,
143 <0x56028 0x4>;
157 clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>;
161 ranges = <0x0 0x56000 0x1000>;
163 sdma: dma-controller@0 {
165 reg = <0x0 0x1000>;
176 target-module@58000 { /* 0x4a058000, ap 10 0e.0 */
178 reg = <0x58000 0x4>,
179 <0x58010 0x4>,
180 <0x58014 0x4>;
195 clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
199 ranges = <0x0 0x58000 0x5000>;
201 hsi: hsi@0 {
203 reg = <0x0 0x4000>,
204 <0x5000 0x1000>;
207 clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
215 ranges = <0 0 0x4000>;
219 reg = <0x2000 0x800>,
220 <0x2800 0x800>;
227 reg = <0x3000 0x800>,
228 <0x3800 0x800>;
235 target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */
240 ranges = <0x0 0x5e000 0x2000>;
243 target-module@62000 { /* 0x4a062000, ap 11 16.0 */
245 reg = <0x62000 0x4>,
246 <0x62010 0x4>,
247 <0x62014 0x4>;
257 clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>;
261 ranges = <0x0 0x62000 0x1000>;
263 usbhstll: usbhstll@0 {
265 reg = <0x0 0x1000>;
270 target-module@64000 { /* 0x4a064000, ap 86 1e.0 */
272 reg = <0x64000 0x4>,
273 <0x64010 0x4>,
274 <0x64014 0x4>;
286 clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>;
290 ranges = <0x0 0x64000 0x1000>;
292 usbhshost: usbhshost@0 {
294 reg = <0x0 0x800>;
297 ranges = <0 0 0x1000>;
307 reg = <0x800 0x400>;
314 reg = <0xc00 0x400>;
320 target-module@66000 { /* 0x4a066000, ap 25 26.0 */
322 reg = <0x66000 0x4>,
323 <0x66010 0x4>,
324 <0x66014 0x4>;
333 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
340 ranges = <0x0 0x66000 0x1000>;
342 mmu_dsp: mmu@0 {
344 reg = <0x0 0x100>;
346 #iommu-cells = <0>;
351 segment@80000 { /* 0x4a080000 */
355 ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
356 <0x0005a000 0x000da000 0x001000>, /* ap 14 */
357 <0x0005b000 0x000db000 0x001000>, /* ap 15 */
358 <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
359 <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
360 <0x0005e000 0x000de000 0x001000>, /* ap 18 */
361 <0x00060000 0x000e0000 0x001000>, /* ap 19 */
362 <0x00061000 0x000e1000 0x001000>, /* ap 20 */
363 <0x00074000 0x000f4000 0x001000>, /* ap 27 */
364 <0x00075000 0x000f5000 0x001000>, /* ap 28 */
365 <0x00076000 0x000f6000 0x001000>, /* ap 29 */
366 <0x00077000 0x000f7000 0x001000>, /* ap 30 */
367 <0x00036000 0x000b6000 0x001000>, /* ap 69 */
368 <0x00037000 0x000b7000 0x001000>, /* ap 70 */
369 <0x0004d000 0x000cd000 0x001000>, /* ap 78 */
370 <0x0004e000 0x000ce000 0x001000>, /* ap 79 */
371 <0x00029000 0x000a9000 0x001000>, /* ap 82 */
372 <0x0002a000 0x000aa000 0x001000>, /* ap 83 */
373 <0x0002b000 0x000ab000 0x001000>, /* ap 84 */
374 <0x0002c000 0x000ac000 0x001000>, /* ap 85 */
375 <0x0002d000 0x000ad000 0x001000>, /* ap 88 */
376 <0x0002e000 0x000ae000 0x001000>; /* ap 89 */
378 target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */
383 ranges = <0x0 0x29000 0x1000>;
386 target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
388 reg = <0x2b400 0x4>,
389 <0x2b404 0x4>,
390 <0x2b408 0x4>;
404 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
408 ranges = <0x0 0x2b000 0x1000>;
410 usb_otg_hs: usb_otg_hs@0 {
412 reg = <0x0 0x7ff>;
425 target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */
427 reg = <0x2d000 0x4>,
428 <0x2d010 0x4>,
429 <0x2d014 0x4>;
438 clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>;
442 ranges = <0x0 0x2d000 0x1000>;
444 ocp2scp@0 {
446 reg = <0x0 0x1f>;
449 ranges = <0 0 0x1000>;
452 reg = <0x80 0x58>;
456 #phy-cells = <0>;
462 target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */
464 reg = <0x36000 0x4>,
465 <0x36010 0x4>,
466 <0x36014 0x4>;
475 clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
479 ranges = <0x0 0x36000 0x1000>;
483 target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */
485 reg = <0x4d000 0x4>,
486 <0x4d010 0x4>,
487 <0x4d014 0x4>;
496 clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
500 ranges = <0x0 0x4d000 0x1000>;
503 target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */
505 reg = <0x59038 0x4>;
513 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>;
517 ranges = <0x0 0x59000 0x1000>;
519 smartreflex_mpu: smartreflex@0 {
521 reg = <0x0 0x80>;
526 target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */
528 reg = <0x5b038 0x4>;
536 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>;
540 ranges = <0x0 0x5b000 0x1000>;
542 smartreflex_iva: smartreflex@0 {
544 reg = <0x0 0x80>;
549 target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */
551 reg = <0x5d038 0x4>;
559 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>;
563 ranges = <0x0 0x5d000 0x1000>;
565 smartreflex_core: smartreflex@0 {
567 reg = <0x0 0x80>;
572 target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */
577 ranges = <0x0 0x60000 0x1000>;
580 target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */
582 reg = <0x74000 0x4>,
583 <0x74010 0x4>;
590 clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>;
594 ranges = <0x0 0x74000 0x1000>;
596 mailbox: mailbox@0 {
598 reg = <0x0 0x200>;
604 ti,mbox-tx = <0 0 0>;
605 ti,mbox-rx = <1 0 0>;
608 ti,mbox-tx = <3 0 0>;
609 ti,mbox-rx = <2 0 0>;
614 target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */
616 reg = <0x76000 0x4>,
617 <0x76010 0x4>,
618 <0x76014 0x4>;
629 clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>;
633 ranges = <0x0 0x76000 0x1000>;
635 hwspinlock: spinlock@0 {
637 reg = <0x0 0x1000>;
643 segment@100000 { /* 0x4a100000 */
647 ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */
648 <0x00001000 0x00101000 0x001000>, /* ap 22 */
649 <0x00002000 0x00102000 0x001000>, /* ap 61 */
650 <0x00003000 0x00103000 0x001000>, /* ap 62 */
651 <0x00008000 0x00108000 0x001000>, /* ap 63 */
652 <0x00009000 0x00109000 0x001000>, /* ap 64 */
653 <0x0000a000 0x0010a000 0x001000>, /* ap 65 */
654 <0x0000b000 0x0010b000 0x001000>; /* ap 66 */
656 target-module@0 { /* 0x4a100000, ap 21 2a.0 */
658 reg = <0x0 0x4>,
659 <0x10 0x4>;
668 ranges = <0x0 0x0 0x1000>;
673 reg = <0x40 0x0196>;
675 #size-cells = <0>;
680 pinctrl-single,function-mask = <0x7fff>;
686 reg = <0x5a0 0x170>;
689 ranges = <0 0x5a0 0x170>;
693 reg = <0x60 0x4>;
704 target-module@2000 { /* 0x4a102000, ap 61 3c.0 */
709 ranges = <0x0 0x2000 0x1000>;
712 target-module@8000 { /* 0x4a108000, ap 63 62.0 */
717 ranges = <0x0 0x8000 0x1000>;
720 target-module@a000 { /* 0x4a10a000, ap 65 50.0 */
722 reg = <0xa000 0x4>,
723 <0xa010 0x4>;
734 clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>;
738 ranges = <0x0 0xa000 0x1000>;
744 segment@180000 { /* 0x4a180000 */
750 segment@200000 { /* 0x4a200000 */
754 ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */
755 <0x0001f000 0x0021f000 0x001000>, /* ap 32 */
756 <0x0000a000 0x0020a000 0x001000>, /* ap 33 */
757 <0x0000b000 0x0020b000 0x001000>, /* ap 34 */
758 <0x00004000 0x00204000 0x001000>, /* ap 35 */
759 <0x00005000 0x00205000 0x001000>, /* ap 36 */
760 <0x00006000 0x00206000 0x001000>, /* ap 37 */
761 <0x00007000 0x00207000 0x001000>, /* ap 38 */
762 <0x00012000 0x00212000 0x001000>, /* ap 39 */
763 <0x00013000 0x00213000 0x001000>, /* ap 40 */
764 <0x0000c000 0x0020c000 0x001000>, /* ap 41 */
765 <0x0000d000 0x0020d000 0x001000>, /* ap 42 */
766 <0x00010000 0x00210000 0x001000>, /* ap 43 */
767 <0x00011000 0x00211000 0x001000>, /* ap 44 */
768 <0x00016000 0x00216000 0x001000>, /* ap 45 */
769 <0x00017000 0x00217000 0x001000>, /* ap 46 */
770 <0x00014000 0x00214000 0x001000>, /* ap 47 */
771 <0x00015000 0x00215000 0x001000>, /* ap 48 */
772 <0x00018000 0x00218000 0x001000>, /* ap 49 */
773 <0x00019000 0x00219000 0x001000>, /* ap 50 */
774 <0x00020000 0x00220000 0x001000>, /* ap 51 */
775 <0x00021000 0x00221000 0x001000>, /* ap 52 */
776 <0x00026000 0x00226000 0x001000>, /* ap 53 */
777 <0x00027000 0x00227000 0x001000>, /* ap 54 */
778 <0x00028000 0x00228000 0x001000>, /* ap 55 */
779 <0x00029000 0x00229000 0x001000>, /* ap 56 */
780 <0x0002a000 0x0022a000 0x001000>, /* ap 57 */
781 <0x0002b000 0x0022b000 0x001000>, /* ap 58 */
782 <0x0001c000 0x0021c000 0x001000>, /* ap 59 */
783 <0x0001d000 0x0021d000 0x001000>; /* ap 60 */
785 target-module@4000 { /* 0x4a204000, ap 35 42.0 */
790 ranges = <0x0 0x4000 0x1000>;
793 target-module@6000 { /* 0x4a206000, ap 37 4a.0 */
798 ranges = <0x0 0x6000 0x1000>;
801 target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */
806 ranges = <0x0 0xa000 0x1000>;
809 target-module@c000 { /* 0x4a20c000, ap 41 20.0 */
814 ranges = <0x0 0xc000 0x1000>;
817 target-module@10000 { /* 0x4a210000, ap 43 52.0 */
822 ranges = <0x0 0x10000 0x1000>;
825 target-module@12000 { /* 0x4a212000, ap 39 18.0 */
830 ranges = <0x0 0x12000 0x1000>;
833 target-module@14000 { /* 0x4a214000, ap 47 30.0 */
838 ranges = <0x0 0x14000 0x1000>;
841 target-module@16000 { /* 0x4a216000, ap 45 28.0 */
846 ranges = <0x0 0x16000 0x1000>;
849 target-module@18000 { /* 0x4a218000, ap 49 38.0 */
854 ranges = <0x0 0x18000 0x1000>;
857 target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */
862 ranges = <0x0 0x1c000 0x1000>;
865 target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */
870 ranges = <0x0 0x1e000 0x1000>;
873 target-module@20000 { /* 0x4a220000, ap 51 40.0 */
878 ranges = <0x0 0x20000 0x1000>;
881 target-module@26000 { /* 0x4a226000, ap 53 34.0 */
886 ranges = <0x0 0x26000 0x1000>;
889 target-module@28000 { /* 0x4a228000, ap 55 2e.0 */
894 ranges = <0x0 0x28000 0x1000>;
897 target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */
902 ranges = <0x0 0x2a000 0x1000>;
906 segment@280000 { /* 0x4a280000 */
912 l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */
916 ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
917 <0x00040000 0x00340000 0x001000>, /* ap 68 */
918 <0x00020000 0x00320000 0x004000>, /* ap 71 */
919 <0x00024000 0x00324000 0x002000>, /* ap 72 */
920 <0x00026000 0x00326000 0x001000>, /* ap 73 */
921 <0x00027000 0x00327000 0x001000>, /* ap 74 */
922 <0x00028000 0x00328000 0x001000>, /* ap 75 */
923 <0x00029000 0x00329000 0x001000>, /* ap 76 */
924 <0x00030000 0x00330000 0x010000>, /* ap 77 */
925 <0x0002a000 0x0032a000 0x002000>, /* ap 90 */
926 <0x0002c000 0x0032c000 0x004000>; /* ap 91 */
928 l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */
933 ranges = <0x00000000 0x00000000 0x00020000>,
934 <0x00020000 0x00020000 0x00004000>,
935 <0x00024000 0x00024000 0x00002000>,
936 <0x00026000 0x00026000 0x00001000>,
937 <0x00027000 0x00027000 0x00001000>,
938 <0x00028000 0x00028000 0x00001000>,
939 <0x00029000 0x00029000 0x00001000>,
940 <0x0002a000 0x0002a000 0x00002000>,
941 <0x0002c000 0x0002c000 0x00004000>,
942 <0x00030000 0x00030000 0x00010000>;
947 &l4_wkup { /* 0x4a300000 */
950 clocks = <&l4_wkup_clkctrl OMAP4_L4_WKUP_CLKCTRL 0>;
952 reg = <0x4a300000 0x800>,
953 <0x4a300800 0x800>,
954 <0x4a301000 0x1000>;
958 ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */
959 <0x00010000 0x4a310000 0x010000>, /* segment 1 */
960 <0x00020000 0x4a320000 0x010000>; /* segment 2 */
962 segment@0 { /* 0x4a300000 */
966 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
967 <0x00001000 0x00001000 0x001000>, /* ap 1 */
968 <0x00000800 0x00000800 0x000800>, /* ap 2 */
969 <0x00006000 0x00006000 0x002000>, /* ap 3 */
970 <0x00008000 0x00008000 0x001000>, /* ap 4 */
971 <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
972 <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
973 <0x00004000 0x00004000 0x001000>, /* ap 17 */
974 <0x00005000 0x00005000 0x001000>, /* ap 18 */
975 <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
976 <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
978 target-module@4000 { /* 0x4a304000, ap 17 24.0 */
980 reg = <0x4000 0x4>,
981 <0x4004 0x4>;
986 clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>;
990 ranges = <0x0 0x4000 0x1000>;
992 counter32k: counter@0 {
994 reg = <0x0 0x20>;
998 target-module@6000 { /* 0x4a306000, ap 3 08.0 */
1000 reg = <0x6000 0x4>;
1004 ranges = <0x0 0x6000 0x2000>;
1006 prm: prm@0 {
1008 reg = <0x0 0x2000>;
1012 ranges = <0 0 0x2000>;
1016 #size-cells = <0>;
1024 target-module@a000 { /* 0x4a30a000, ap 15 34.0 */
1026 reg = <0xa000 0x4>;
1030 ranges = <0x0 0xa000 0x1000>;
1032 scrm: scrm@0 {
1034 reg = <0x0 0x2000>;
1038 #size-cells = <0>;
1046 target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */
1048 reg = <0xc000 0x4>,
1049 <0xc010 0x4>;
1058 ranges = <0x0 0xc000 0x1000>;
1062 reg = <0xc000 0x1000>;
1067 segment@10000 { /* 0x4a310000 */
1071 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
1072 <0x00001000 0x00011000 0x001000>, /* ap 6 */
1073 <0x00004000 0x00014000 0x001000>, /* ap 7 */
1074 <0x00005000 0x00015000 0x001000>, /* ap 8 */
1075 <0x00008000 0x00018000 0x001000>, /* ap 9 */
1076 <0x00009000 0x00019000 0x001000>, /* ap 10 */
1077 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
1078 <0x0000d000 0x0001d000 0x001000>, /* ap 12 */
1079 <0x0000e000 0x0001e000 0x001000>, /* ap 21 */
1080 <0x0000f000 0x0001f000 0x001000>; /* ap 22 */
1082 gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */
1084 reg = <0x0 0x4>,
1085 <0x10 0x4>,
1086 <0x114 0x4>;
1097 clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>,
1102 ranges = <0x0 0x0 0x1000>;
1104 gpio1: gpio@0 {
1106 reg = <0x0 0x200>;
1116 target-module@4000 { /* 0x4a314000, ap 7 18.0 */
1118 reg = <0x4000 0x4>,
1119 <0x4010 0x4>,
1120 <0x4014 0x4>;
1130 clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>;
1134 ranges = <0x0 0x4000 0x1000>;
1136 wdt2: wdt@0 {
1138 reg = <0x0 0x80>;
1143 timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
1145 reg = <0x8000 0x4>,
1146 <0x8010 0x4>,
1147 <0x8014 0x4>;
1159 clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>;
1163 ranges = <0x0 0x8000 0x1000>;
1165 timer1: timer@0 {
1167 reg = <0x0 0x80>;
1176 target-module@c000 { /* 0x4a31c000, ap 11 20.0 */
1178 reg = <0xc000 0x4>,
1179 <0xc010 0x4>,
1180 <0xc014 0x4>;
1192 clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>;
1196 ranges = <0x0 0xc000 0x1000>;
1198 keypad: keypad@0 {
1200 reg = <0x0 0x80>;
1206 target-module@e000 { /* 0x4a31e000, ap 21 30.0 */
1208 reg = <0xe000 0x4>,
1209 <0xe010 0x4>;
1218 ranges = <0x0 0xe000 0x1000>;
1223 reg = <0x40 0x0038>;
1225 #size-cells = <0>;
1230 pinctrl-single,function-mask = <0x7fff>;
1235 segment@20000 { /* 0x4a320000 */
1239 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
1240 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
1241 <0x00000000 0x00020000 0x001000>, /* ap 23 */
1242 <0x00001000 0x00021000 0x001000>, /* ap 24 */
1243 <0x00002000 0x00022000 0x001000>, /* ap 25 */
1244 <0x00003000 0x00023000 0x001000>, /* ap 26 */
1245 <0x00004000 0x00024000 0x001000>, /* ap 27 */
1246 <0x00005000 0x00025000 0x001000>, /* ap 28 */
1247 <0x00007000 0x00027000 0x000400>, /* ap 29 */
1248 <0x00008000 0x00028000 0x000800>, /* ap 30 */
1249 <0x00009000 0x00029000 0x000400>; /* ap 31 */
1251 target-module@0 { /* 0x4a320000, ap 23 04.0 */
1256 ranges = <0x0 0x0 0x1000>;
1259 target-module@2000 { /* 0x4a322000, ap 25 0c.0 */
1264 ranges = <0x0 0x2000 0x1000>;
1267 target-module@4000 { /* 0x4a324000, ap 27 10.0 */
1272 ranges = <0x0 0x4000 0x1000>;
1275 target-module@6000 { /* 0x4a326000, ap 13 28.0 */
1280 ranges = <0x00000000 0x00006000 0x00001000>,
1281 <0x00001000 0x00007000 0x00000400>,
1282 <0x00002000 0x00008000 0x00000800>,
1283 <0x00003000 0x00009000 0x00000400>;
1288 &l4_per { /* 0x48000000 */
1291 clocks = <&l4_per_clkctrl OMAP4_L4_PER_CLKCTRL 0>;
1293 reg = <0x48000000 0x800>,
1294 <0x48000800 0x800>,
1295 <0x48001000 0x400>,
1296 <0x48001400 0x400>,
1297 <0x48001800 0x400>,
1298 <0x48001c00 0x400>;
1302 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
1303 <0x00200000 0x48200000 0x200000>; /* segment 1 */
1305 segment@0 { /* 0x48000000 */
1309 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1310 <0x00001000 0x00001000 0x000400>, /* ap 1 */
1311 <0x00000800 0x00000800 0x000800>, /* ap 2 */
1312 <0x00020000 0x00020000 0x001000>, /* ap 3 */
1313 <0x00021000 0x00021000 0x001000>, /* ap 4 */
1314 <0x00032000 0x00032000 0x001000>, /* ap 5 */
1315 <0x00033000 0x00033000 0x001000>, /* ap 6 */
1316 <0x00034000 0x00034000 0x001000>, /* ap 7 */
1317 <0x00035000 0x00035000 0x001000>, /* ap 8 */
1318 <0x00036000 0x00036000 0x001000>, /* ap 9 */
1319 <0x00037000 0x00037000 0x001000>, /* ap 10 */
1320 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
1321 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
1322 <0x00040000 0x00040000 0x010000>, /* ap 13 */
1323 <0x00050000 0x00050000 0x001000>, /* ap 14 */
1324 <0x00055000 0x00055000 0x001000>, /* ap 15 */
1325 <0x00056000 0x00056000 0x001000>, /* ap 16 */
1326 <0x00057000 0x00057000 0x001000>, /* ap 17 */
1327 <0x00058000 0x00058000 0x001000>, /* ap 18 */
1328 <0x00059000 0x00059000 0x001000>, /* ap 19 */
1329 <0x0005a000 0x0005a000 0x001000>, /* ap 20 */
1330 <0x0005b000 0x0005b000 0x001000>, /* ap 21 */
1331 <0x0005c000 0x0005c000 0x001000>, /* ap 22 */
1332 <0x0005d000 0x0005d000 0x001000>, /* ap 23 */
1333 <0x0005e000 0x0005e000 0x001000>, /* ap 24 */
1334 <0x00060000 0x00060000 0x001000>, /* ap 25 */
1335 <0x0006a000 0x0006a000 0x001000>, /* ap 26 */
1336 <0x0006b000 0x0006b000 0x001000>, /* ap 27 */
1337 <0x0006c000 0x0006c000 0x001000>, /* ap 28 */
1338 <0x0006d000 0x0006d000 0x001000>, /* ap 29 */
1339 <0x0006e000 0x0006e000 0x001000>, /* ap 30 */
1340 <0x0006f000 0x0006f000 0x001000>, /* ap 31 */
1341 <0x00070000 0x00070000 0x001000>, /* ap 32 */
1342 <0x00071000 0x00071000 0x001000>, /* ap 33 */
1343 <0x00072000 0x00072000 0x001000>, /* ap 34 */
1344 <0x00073000 0x00073000 0x001000>, /* ap 35 */
1345 <0x00061000 0x00061000 0x001000>, /* ap 36 */
1346 <0x00096000 0x00096000 0x001000>, /* ap 37 */
1347 <0x00097000 0x00097000 0x001000>, /* ap 38 */
1348 <0x00076000 0x00076000 0x001000>, /* ap 39 */
1349 <0x00077000 0x00077000 0x001000>, /* ap 40 */
1350 <0x00078000 0x00078000 0x001000>, /* ap 41 */
1351 <0x00079000 0x00079000 0x001000>, /* ap 42 */
1352 <0x00086000 0x00086000 0x001000>, /* ap 43 */
1353 <0x00087000 0x00087000 0x001000>, /* ap 44 */
1354 <0x00088000 0x00088000 0x001000>, /* ap 45 */
1355 <0x00089000 0x00089000 0x001000>, /* ap 46 */
1356 <0x000b0000 0x000b0000 0x001000>, /* ap 47 */
1357 <0x000b1000 0x000b1000 0x001000>, /* ap 48 */
1358 <0x00098000 0x00098000 0x001000>, /* ap 49 */
1359 <0x00099000 0x00099000 0x001000>, /* ap 50 */
1360 <0x0009a000 0x0009a000 0x001000>, /* ap 51 */
1361 <0x0009b000 0x0009b000 0x001000>, /* ap 52 */
1362 <0x0009c000 0x0009c000 0x001000>, /* ap 53 */
1363 <0x0009d000 0x0009d000 0x001000>, /* ap 54 */
1364 <0x0009e000 0x0009e000 0x001000>, /* ap 55 */
1365 <0x0009f000 0x0009f000 0x001000>, /* ap 56 */
1366 <0x00090000 0x00090000 0x002000>, /* ap 57 */
1367 <0x00092000 0x00092000 0x001000>, /* ap 58 */
1368 <0x000a4000 0x000a4000 0x001000>, /* ap 59 */
1369 <0x000a6000 0x000a6000 0x001000>, /* ap 60 */
1370 <0x000a8000 0x000a8000 0x004000>, /* ap 61 */
1371 <0x000ac000 0x000ac000 0x001000>, /* ap 62 */
1372 <0x000ad000 0x000ad000 0x001000>, /* ap 63 */
1373 <0x000ae000 0x000ae000 0x001000>, /* ap 64 */
1374 <0x000b2000 0x000b2000 0x001000>, /* ap 65 */
1375 <0x000b3000 0x000b3000 0x001000>, /* ap 66 */
1376 <0x000b4000 0x000b4000 0x001000>, /* ap 67 */
1377 <0x000b5000 0x000b5000 0x001000>, /* ap 68 */
1378 <0x000b8000 0x000b8000 0x001000>, /* ap 69 */
1379 <0x000b9000 0x000b9000 0x001000>, /* ap 70 */
1380 <0x000ba000 0x000ba000 0x001000>, /* ap 71 */
1381 <0x000bb000 0x000bb000 0x001000>, /* ap 72 */
1382 <0x000d1000 0x000d1000 0x001000>, /* ap 73 */
1383 <0x000d2000 0x000d2000 0x001000>, /* ap 74 */
1384 <0x000d5000 0x000d5000 0x001000>, /* ap 75 */
1385 <0x000d6000 0x000d6000 0x001000>, /* ap 76 */
1386 <0x000a2000 0x000a2000 0x001000>, /* ap 79 */
1387 <0x000a3000 0x000a3000 0x001000>, /* ap 80 */
1388 <0x00001400 0x00001400 0x000400>, /* ap 81 */
1389 <0x00001800 0x00001800 0x000400>, /* ap 82 */
1390 <0x00001c00 0x00001c00 0x000400>, /* ap 83 */
1391 <0x000a5000 0x000a5000 0x001000>; /* ap 84 */
1393 target-module@20000 { /* 0x48020000, ap 3 06.0 */
1395 reg = <0x20050 0x4>,
1396 <0x20054 0x4>,
1397 <0x20058 0x4>;
1408 clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>;
1412 ranges = <0x0 0x20000 0x1000>;
1414 uart3: serial@0 {
1416 reg = <0x0 0x100>;
1422 target-module@32000 { /* 0x48032000, ap 5 02.0 */
1424 reg = <0x32000 0x4>,
1425 <0x32010 0x4>,
1426 <0x32014 0x4>;
1438 clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>;
1442 ranges = <0x0 0x32000 0x1000>;
1444 timer2: timer@0 {
1446 reg = <0x0 0x80>;
1454 target-module@34000 { /* 0x48034000, ap 7 04.0 */
1456 reg = <0x34000 0x4>,
1457 <0x34010 0x4>;
1466 clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>;
1470 ranges = <0x0 0x34000 0x1000>;
1472 timer3: timer@0 {
1474 reg = <0x0 0x80>;
1482 target-module@36000 { /* 0x48036000, ap 9 0e.0 */
1484 reg = <0x36000 0x4>,
1485 <0x36010 0x4>;
1494 clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>;
1498 ranges = <0x0 0x36000 0x1000>;
1500 timer4: timer@0 {
1502 reg = <0x0 0x80>;
1510 target-module@3e000 { /* 0x4803e000, ap 11 08.0 */
1512 reg = <0x3e000 0x4>,
1513 <0x3e010 0x4>;
1522 clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>;
1526 ranges = <0x0 0x3e000 0x1000>;
1528 timer9: timer@0 {
1530 reg = <0x0 0x80>;
1540 target-module@40000 { /* 0x48040000, ap 13 0a.0 */
1545 ranges = <0x0 0x40000 0x10000>;
1548 target-module@55000 { /* 0x48055000, ap 15 0c.0 */
1550 reg = <0x55000 0x4>,
1551 <0x55010 0x4>,
1552 <0x55114 0x4>;
1563 clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>,
1568 ranges = <0x0 0x55000 0x1000>;
1570 gpio2: gpio@0 {
1572 reg = <0x0 0x200>;
1581 target-module@57000 { /* 0x48057000, ap 17 16.0 */
1583 reg = <0x57000 0x4>,
1584 <0x57010 0x4>,
1585 <0x57114 0x4>;
1596 clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>,
1601 ranges = <0x0 0x57000 0x1000>;
1603 gpio3: gpio@0 {
1605 reg = <0x0 0x200>;
1614 target-module@59000 { /* 0x48059000, ap 19 10.0 */
1616 reg = <0x59000 0x4>,
1617 <0x59010 0x4>,
1618 <0x59114 0x4>;
1629 clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>,
1634 ranges = <0x0 0x59000 0x1000>;
1636 gpio4: gpio@0 {
1638 reg = <0x0 0x200>;
1647 target-module@5b000 { /* 0x4805b000, ap 21 12.0 */
1649 reg = <0x5b000 0x4>,
1650 <0x5b010 0x4>,
1651 <0x5b114 0x4>;
1662 clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>,
1667 ranges = <0x0 0x5b000 0x1000>;
1669 gpio5: gpio@0 {
1671 reg = <0x0 0x200>;
1680 target-module@5d000 { /* 0x4805d000, ap 23 14.0 */
1682 reg = <0x5d000 0x4>,
1683 <0x5d010 0x4>,
1684 <0x5d114 0x4>;
1695 clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>,
1700 ranges = <0x0 0x5d000 0x1000>;
1702 gpio6: gpio@0 {
1704 reg = <0x0 0x200>;
1713 target-module@60000 { /* 0x48060000, ap 25 1e.0 */
1715 reg = <0x60000 0x8>,
1716 <0x60010 0x8>,
1717 <0x60090 0x8>;
1729 clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>;
1733 ranges = <0x0 0x60000 0x1000>;
1735 i2c3: i2c@0 {
1737 reg = <0x0 0x100>;
1740 #size-cells = <0>;
1744 target-module@6a000 { /* 0x4806a000, ap 26 18.0 */
1746 reg = <0x6a050 0x4>,
1747 <0x6a054 0x4>,
1748 <0x6a058 0x4>;
1759 clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>;
1763 ranges = <0x0 0x6a000 0x1000>;
1765 uart1: serial@0 {
1767 reg = <0x0 0x100>;
1773 target-module@6c000 { /* 0x4806c000, ap 28 20.0 */
1775 reg = <0x6c050 0x4>,
1776 <0x6c054 0x4>,
1777 <0x6c058 0x4>;
1788 clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>;
1792 ranges = <0x0 0x6c000 0x1000>;
1794 uart2: serial@0 {
1796 reg = <0x0 0x100>;
1802 target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */
1804 reg = <0x6e050 0x4>,
1805 <0x6e054 0x4>,
1806 <0x6e058 0x4>;
1817 clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>;
1821 ranges = <0x0 0x6e000 0x1000>;
1823 uart4: serial@0 {
1825 reg = <0x0 0x100>;
1831 target-module@70000 { /* 0x48070000, ap 32 28.0 */
1833 reg = <0x70000 0x8>,
1834 <0x70010 0x8>,
1835 <0x70090 0x8>;
1847 clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>;
1851 ranges = <0x0 0x70000 0x1000>;
1853 i2c1: i2c@0 {
1855 reg = <0x0 0x100>;
1858 #size-cells = <0>;
1862 target-module@72000 { /* 0x48072000, ap 34 30.0 */
1864 reg = <0x72000 0x8>,
1865 <0x72010 0x8>,
1866 <0x72090 0x8>;
1878 clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>;
1882 ranges = <0x0 0x72000 0x1000>;
1884 i2c2: i2c@0 {
1886 reg = <0x0 0x100>;
1889 #size-cells = <0>;
1893 target-module@76000 { /* 0x48076000, ap 39 38.0 */
1895 reg = <0x76000 0x4>,
1896 <0x76010 0x4>;
1904 clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>;
1908 ranges = <0x0 0x76000 0x1000>;
1913 target-module@78000 { /* 0x48078000, ap 41 1a.0 */
1915 reg = <0x78000 0x4>,
1916 <0x78010 0x4>,
1917 <0x78014 0x4>;
1927 clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>;
1931 ranges = <0x0 0x78000 0x1000>;
1933 elm: elm@0 {
1935 reg = <0x0 0x2000>;
1941 target-module@86000 { /* 0x48086000, ap 43 24.0 */
1943 reg = <0x86000 0x4>,
1944 <0x86010 0x4>,
1945 <0x86014 0x4>;
1957 clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>;
1961 ranges = <0x0 0x86000 0x1000>;
1963 timer10: timer@0 {
1965 reg = <0x0 0x80>;
1974 target-module@88000 { /* 0x48088000, ap 45 2e.0 */
1976 reg = <0x88000 0x4>,
1977 <0x88010 0x4>;
1986 clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>;
1990 ranges = <0x0 0x88000 0x1000>;
1992 timer11: timer@0 {
1994 reg = <0x0 0x80>;
2003 rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */
2005 reg = <0x91fe0 0x4>,
2006 <0x91fe4 0x4>;
2012 clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>;
2016 ranges = <0x0 0x90000 0x2000>;
2018 rng: rng@0 {
2020 reg = <0x0 0x2000>;
2025 target-module@96000 { /* 0x48096000, ap 37 26.0 */
2027 reg = <0x9608c 0x4>;
2036 clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>;
2040 ranges = <0x0 0x96000 0x1000>;
2042 mcbsp4: mcbsp@0 {
2044 reg = <0x0 0xff>; /* L4 Interconnect */
2058 target-module@98000 { /* 0x48098000, ap 49 22.0 */
2060 reg = <0x98000 0x4>,
2061 <0x98010 0x4>;
2070 clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>;
2074 ranges = <0x0 0x98000 0x1000>;
2076 mcspi1: spi@0 {
2078 reg = <0x0 0x200>;
2081 #size-cells = <0>;
2096 target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */
2098 reg = <0x9a000 0x4>,
2099 <0x9a010 0x4>;
2108 clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>;
2112 ranges = <0x0 0x9a000 0x1000>;
2114 mcspi2: spi@0 {
2116 reg = <0x0 0x200>;
2119 #size-cells = <0>;
2129 target-module@9c000 { /* 0x4809c000, ap 53 36.0 */
2131 reg = <0x9c000 0x4>,
2132 <0x9c010 0x4>;
2145 clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>;
2149 ranges = <0x0 0x9c000 0x1000>;
2151 mmc1: mmc@0 {
2153 reg = <0x0 0x400>;
2163 target-module@9e000 { /* 0x4809e000, ap 55 48.0 */
2168 ranges = <0x0 0x9e000 0x1000>;
2171 target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */
2176 ranges = <0x0 0xa2000 0x1000>;
2179 target-module@a4000 { /* 0x480a4000, ap 59 34.0 */
2184 ranges = <0x00000000 0x000a4000 0x00001000>,
2185 <0x00001000 0x000a5000 0x00001000>;
2188 des_target: target-module@a5000 { /* 0x480a5000 */
2190 reg = <0xa5030 0x4>,
2191 <0xa5034 0x4>,
2192 <0xa5038 0x4>;
2202 clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>;
2206 ranges = <0 0xa5000 0x00001000>;
2208 des: des@0 {
2210 reg = <0 0xa0>;
2217 target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */
2222 ranges = <0x0 0xa8000 0x4000>;
2225 target-module@ad000 { /* 0x480ad000, ap 63 50.0 */
2227 reg = <0xad000 0x4>,
2228 <0xad010 0x4>;
2241 clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>;
2245 ranges = <0x0 0xad000 0x1000>;
2247 mmc3: mmc@0 {
2249 reg = <0x0 0x400>;
2257 target-module@b0000 { /* 0x480b0000, ap 47 40.0 */
2262 ranges = <0x0 0xb0000 0x1000>;
2265 target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */
2267 reg = <0xb2000 0x4>,
2268 <0xb2014 0x4>,
2269 <0xb2018 0x4>;
2276 clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>;
2280 ranges = <0x0 0xb2000 0x1000>;
2282 hdqw1w: 1w@0 {
2284 reg = <0x0 0x1000>;
2289 target-module@b4000 { /* 0x480b4000, ap 67 46.0 */
2291 reg = <0xb4000 0x4>,
2292 <0xb4010 0x4>;
2305 clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>;
2309 ranges = <0x0 0xb4000 0x1000>;
2311 mmc2: mmc@0 {
2313 reg = <0x0 0x400>;
2321 target-module@b8000 { /* 0x480b8000, ap 69 58.0 */
2323 reg = <0xb8000 0x4>,
2324 <0xb8010 0x4>;
2333 clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>;
2337 ranges = <0x0 0xb8000 0x1000>;
2339 mcspi3: spi@0 {
2341 reg = <0x0 0x200>;
2344 #size-cells = <0>;
2351 target-module@ba000 { /* 0x480ba000, ap 71 32.0 */
2353 reg = <0xba000 0x4>,
2354 <0xba010 0x4>;
2363 clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>;
2367 ranges = <0x0 0xba000 0x1000>;
2369 mcspi4: spi@0 {
2371 reg = <0x0 0x200>;
2374 #size-cells = <0>;
2381 target-module@d1000 { /* 0x480d1000, ap 73 44.0 */
2383 reg = <0xd1000 0x4>,
2384 <0xd1010 0x4>;
2397 clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>;
2401 ranges = <0x0 0xd1000 0x1000>;
2403 mmc4: mmc@0 {
2405 reg = <0x0 0x400>;
2413 target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */
2415 reg = <0xd5000 0x4>,
2416 <0xd5010 0x4>;
2429 clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>;
2433 ranges = <0x0 0xd5000 0x1000>;
2435 mmc5: mmc@0 {
2437 reg = <0x0 0x400>;
2446 segment@200000 { /* 0x48200000 */
2450 ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */
2451 <0x00151000 0x00351000 0x001000>; /* ap 78 */
2453 target-module@150000 { /* 0x48350000, ap 77 4c.0 */
2455 reg = <0x150000 0x8>,
2456 <0x150010 0x8>,
2457 <0x150090 0x8>;
2469 clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>;
2473 ranges = <0x0 0x150000 0x1000>;
2475 i2c4: i2c@0 {
2477 reg = <0x0 0x100>;
2480 #size-cells = <0>;