Lines Matching +full:syscon +full:- +full:chipselects
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
48 compatible = "arm,armv7-timer";
54 interrupt-parent = <&gic>;
57 gic: interrupt-controller@48211000 {
58 compatible = "arm,cortex-a15-gic";
59 interrupt-controller;
60 #interrupt-cells = <3>;
66 interrupt-parent = <&gic>;
69 wakeupgen: interrupt-controller@48281000 {
70 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
71 interrupt-controller;
72 #interrupt-cells = <3>;
74 interrupt-parent = <&gic>;
78 #address-cells = <1>;
79 #size-cells = <0>;
83 compatible = "arm,cortex-a15";
86 operating-points-v2 = <&cpu0_opp_table>;
89 clock-names = "cpu";
91 clock-latency = <300000>; /* From omap-cpufreq driver */
94 #cooling-cells = <2>; /* min followed by max */
96 vbb-supply = <&abb_mpu>;
100 cpu0_opp_table: opp-table {
101 compatible = "operating-points-v2-ti-cpu";
102 syscon = <&scm_wkup>;
104 opp-1000000000 {
106 opp-hz = /bits/ 64 <1000000000>;
107 opp-microvolt = <1060000 850000 1150000>,
109 opp-supported-hw = <0xFF 0x01>;
110 opp-suspend;
113 opp-1176000000 {
115 opp-hz = /bits/ 64 <1176000000>;
116 opp-microvolt = <1160000 885000 1160000>,
119 opp-supported-hw = <0xFF 0x02>;
122 opp-1500000000 {
124 opp-hz = /bits/ 64 <1500000000>;
125 opp-microvolt = <1210000 950000 1250000>,
127 opp-supported-hw = <0xFF 0x04>;
139 compatible = "simple-pm-bus";
140 power-domains = <&prm_core>;
143 #address-cells = <1>;
144 #size-cells = <1>;
146 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
148 l3-noc@44000000 {
149 compatible = "ti,dra7-l3-noc";
152 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
163 target-module@48210000 {
164 compatible = "ti,sysc-omap4-simple", "ti,sysc";
165 power-domains = <&prm_mpu>;
167 clock-names = "fck";
168 #address-cells = <1>;
169 #size-cells = <1>;
173 compatible = "ti,omap5-mpu";
185 * 26-678. Main Sequence PCIe Controller Global Initialization"
188 axi0: target-module@51000000 {
189 compatible = "ti,sysc-omap4", "ti,sysc";
190 power-domains = <&prm_l3init>;
192 reset-names = "rstctrl";
196 clock-names = "fck", "phy-clk", "phy-clk-div";
197 #size-cells = <1>;
198 #address-cells = <1>;
201 dma-ranges;
210 reg-names = "rc_dbics", "ti_conf", "config";
212 #address-cells = <3>;
213 #size-cells = <2>;
217 bus-range = <0x00 0xff>;
218 #interrupt-cells = <1>;
219 num-lanes = <1>;
220 linux,pci-domain = <0>;
222 phy-names = "pcie-phy0";
223 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
224 interrupt-map-mask = <0 0 0 7>;
225 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
229 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
231 pcie1_intc: interrupt-controller {
232 interrupt-controller;
233 #address-cells = <0>;
234 #interrupt-cells = <1>;
243 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
245 num-lanes = <1>;
246 num-ib-windows = <4>;
247 num-ob-windows = <16>;
249 phy-names = "pcie-phy0";
250 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
251 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
259 * 26-678. Main Sequence PCIe Controller Global Initialization"
262 axi1: target-module@51800000 {
263 compatible = "ti,sysc-omap4", "ti,sysc";
267 clock-names = "fck", "phy-clk", "phy-clk-div";
268 power-domains = <&prm_l3init>;
270 reset-names = "rstctrl";
271 #size-cells = <1>;
272 #address-cells = <1>;
275 dma-ranges;
281 reg-names = "rc_dbics", "ti_conf", "config";
283 #address-cells = <3>;
284 #size-cells = <2>;
288 bus-range = <0x00 0xff>;
289 #interrupt-cells = <1>;
290 num-lanes = <1>;
291 linux,pci-domain = <1>;
293 phy-names = "pcie-phy0";
294 interrupt-map-mask = <0 0 0 7>;
295 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
299 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
300 pcie2_intc: interrupt-controller {
301 interrupt-controller;
302 #address-cells = <0>;
303 #interrupt-cells = <1>;
309 compatible = "mmio-sram";
312 #address-cells = <1>;
313 #size-cells = <1>;
325 sram-hs@0 {
326 compatible = "ti,secure-ram";
339 compatible = "mmio-sram";
342 #address-cells = <1>;
343 #size-cells = <1>;
348 compatible = "mmio-sram";
351 #address-cells = <1>;
352 #size-cells = <1>;
362 compatible = "ti,dra752-bandgap";
364 #thermal-sensor-cells = <1>;
368 compatible = "syscon";
373 compatible = "ti,dra7-iodelay";
375 #address-cells = <1>;
376 #size-cells = <0>;
377 #pinctrl-cells = <2>;
380 target-module@43300000 {
381 compatible = "ti,sysc-omap4", "ti,sysc";
384 reg-names = "rev", "sysc";
385 ti,sysc-midle = <SYSC_IDLE_FORCE>,
388 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
392 clock-names = "fck";
393 #address-cells = <1>;
394 #size-cells = <1>;
398 compatible = "ti,edma3-tpcc";
400 reg-names = "edma3_cc";
404 interrupt-names = "edma3_ccint", "edma3_mperr",
406 dma-requests = <64>;
407 #dma-cells = <2>;
413 * ti,edma-memcpy-channels = <20 21>;
420 target-module@43400000 {
421 compatible = "ti,sysc-omap4", "ti,sysc";
424 reg-names = "rev", "sysc";
425 ti,sysc-midle = <SYSC_IDLE_FORCE>,
428 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
432 clock-names = "fck";
433 #address-cells = <1>;
434 #size-cells = <1>;
438 compatible = "ti,edma3-tptc";
441 interrupt-names = "edma3_tcerrint";
445 target-module@43500000 {
446 compatible = "ti,sysc-omap4", "ti,sysc";
449 reg-names = "rev", "sysc";
450 ti,sysc-midle = <SYSC_IDLE_FORCE>,
453 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
457 clock-names = "fck";
458 #address-cells = <1>;
459 #size-cells = <1>;
463 compatible = "ti,edma3-tptc";
466 interrupt-names = "edma3_tcerrint";
470 target-module@4e000000 {
471 compatible = "ti,sysc-omap2", "ti,sysc";
474 reg-names = "rev", "sysc";
475 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
479 #size-cells = <1>;
480 #address-cells = <1>;
483 compatible = "ti,omap5-dmm";
490 compatible = "ti,dra7-ipu";
492 reg-names = "l2ram";
497 firmware-name = "dra7-ipu1-fw.xem4";
501 compatible = "ti,dra7-ipu";
503 reg-names = "l2ram";
508 firmware-name = "dra7-ipu2-fw.xem4";
512 compatible = "ti,dra7-dsp";
516 reg-names = "l2ram", "l1pram", "l1dram";
522 firmware-name = "dra7-dsp1-fw.xe66";
525 target-module@40d01000 {
526 compatible = "ti,sysc-omap2", "ti,sysc";
530 reg-names = "rev", "sysc", "syss";
531 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
534 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
538 clock-names = "fck";
540 reset-names = "rstctrl";
542 #size-cells = <1>;
543 #address-cells = <1>;
546 compatible = "ti,dra7-dsp-iommu";
549 #iommu-cells = <0>;
550 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
554 target-module@40d02000 {
555 compatible = "ti,sysc-omap2", "ti,sysc";
559 reg-names = "rev", "sysc", "syss";
560 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
563 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
567 clock-names = "fck";
569 reset-names = "rstctrl";
571 #size-cells = <1>;
572 #address-cells = <1>;
575 compatible = "ti,dra7-dsp-iommu";
578 #iommu-cells = <0>;
579 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
583 target-module@58882000 {
584 compatible = "ti,sysc-omap2", "ti,sysc";
588 reg-names = "rev", "sysc", "syss";
589 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
592 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
596 clock-names = "fck";
598 reset-names = "rstctrl";
599 #address-cells = <1>;
600 #size-cells = <1>;
604 compatible = "ti,dra7-iommu";
607 #iommu-cells = <0>;
608 ti,iommu-bus-err-back;
612 target-module@55082000 {
613 compatible = "ti,sysc-omap2", "ti,sysc";
617 reg-names = "rev", "sysc", "syss";
618 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
621 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
625 clock-names = "fck";
627 reset-names = "rstctrl";
628 #address-cells = <1>;
629 #size-cells = <1>;
633 compatible = "ti,dra7-iommu";
636 #iommu-cells = <0>;
637 ti,iommu-bus-err-back;
641 abb_mpu: regulator-abb-mpu@4ae07ddc {
642 compatible = "ti,abb-v3";
643 regulator-name = "abb_mpu";
644 #address-cells = <0>;
645 #size-cells = <0>;
647 ti,settling-time = <50>;
648 ti,clock-cycles = <16>;
653 reg-names = "setup-address", "control-address",
654 "int-address", "efuse-address",
655 "ldo-address";
656 ti,tranxdone-status-mask = <0x80>;
658 ti,ldovbb-override-mask = <0x400>;
660 ti,ldovbb-vset-mask = <0x1F>;
674 abb_ivahd: regulator-abb-ivahd@4ae07e34 {
675 compatible = "ti,abb-v3";
676 regulator-name = "abb_ivahd";
677 #address-cells = <0>;
678 #size-cells = <0>;
680 ti,settling-time = <50>;
681 ti,clock-cycles = <16>;
686 reg-names = "setup-address", "control-address",
687 "int-address", "efuse-address",
688 "ldo-address";
689 ti,tranxdone-status-mask = <0x40000000>;
691 ti,ldovbb-override-mask = <0x400>;
693 ti,ldovbb-vset-mask = <0x1F>;
707 abb_dspeve: regulator-abb-dspeve@4ae07e30 {
708 compatible = "ti,abb-v3";
709 regulator-name = "abb_dspeve";
710 #address-cells = <0>;
711 #size-cells = <0>;
713 ti,settling-time = <50>;
714 ti,clock-cycles = <16>;
719 reg-names = "setup-address", "control-address",
720 "int-address", "efuse-address",
721 "ldo-address";
722 ti,tranxdone-status-mask = <0x20000000>;
724 ti,ldovbb-override-mask = <0x400>;
726 ti,ldovbb-vset-mask = <0x1F>;
740 abb_gpu: regulator-abb-gpu@4ae07de4 {
741 compatible = "ti,abb-v3";
742 regulator-name = "abb_gpu";
743 #address-cells = <0>;
744 #size-cells = <0>;
746 ti,settling-time = <50>;
747 ti,clock-cycles = <16>;
752 reg-names = "setup-address", "control-address",
753 "int-address", "efuse-address",
754 "ldo-address";
755 ti,tranxdone-status-mask = <0x10000000>;
757 ti,ldovbb-override-mask = <0x400>;
759 ti,ldovbb-vset-mask = <0x1F>;
773 target-module@4b300000 {
774 compatible = "ti,sysc-omap4", "ti,sysc";
777 reg-names = "rev", "sysc";
778 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
783 clock-names = "fck";
784 #address-cells = <1>;
785 #size-cells = <1>;
790 compatible = "ti,dra7xxx-qspi";
793 reg-names = "qspi_base", "qspi_mmap";
794 syscon-chipselects = <&scm_conf 0x558>;
795 #address-cells = <1>;
796 #size-cells = <0>;
798 clock-names = "fck";
799 num-cs = <4>;
808 target-module@50000000 {
809 compatible = "ti,sysc-omap2", "ti,sysc";
813 reg-names = "rev", "sysc", "syss";
814 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
817 ti,syss-mask = <1>;
819 clock-names = "fck";
820 #address-cells = <1>;
821 #size-cells = <1>;
826 compatible = "ti,am3352-gpmc";
830 dma-names = "rxtx";
831 gpmc,num-cs = <8>;
832 gpmc,num-waitpins = <2>;
833 #address-cells = <2>;
834 #size-cells = <1>;
835 interrupt-controller;
836 #interrupt-cells = <2>;
837 gpio-controller;
838 #gpio-cells = <2>;
843 target-module@56000000 {
844 compatible = "ti,sysc-omap4", "ti,sysc";
847 reg-names = "rev", "sysc";
848 ti,sysc-midle = <SYSC_IDLE_FORCE>,
851 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
856 clock-names = "fck";
857 #address-cells = <1>;
858 #size-cells = <1>;
862 compatible = "ti,am5728-gpu", "img,powervr-sgx544";
869 compatible = "ti,irq-crossbar";
871 interrupt-controller;
872 interrupt-parent = <&wakeupgen>;
873 #interrupt-cells = <3>;
874 ti,max-irqs = <160>;
875 ti,max-crossbar-sources = <MAX_SOURCES>;
876 ti,reg-size = <2>;
877 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
878 ti,irqs-skip = <10 133 139 140>;
879 ti,irqs-safe-map = <0>;
882 target-module@58000000 {
883 compatible = "ti,sysc-omap2", "ti,sysc";
886 reg-names = "rev", "syss";
887 ti,syss-mask = <1>;
892 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
893 #address-cells = <1>;
894 #size-cells = <1>;
898 compatible = "ti,dra7-dss";
903 syscon-pll-ctrl = <&scm_conf 0x538>;
904 #address-cells = <1>;
905 #size-cells = <1>;
908 target-module@1000 {
909 compatible = "ti,sysc-omap2", "ti,sysc";
913 reg-names = "rev", "sysc", "syss";
914 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
917 ti,sysc-midle = <SYSC_IDLE_FORCE>,
920 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
924 ti,syss-mask = <1>;
926 clock-names = "fck";
927 #address-cells = <1>;
928 #size-cells = <1>;
932 compatible = "ti,dra7-dispc";
936 clock-names = "fck";
938 syscon-pol = <&scm_conf 0x534>;
942 target-module@40000 {
943 compatible = "ti,sysc-omap4", "ti,sysc";
946 reg-names = "rev", "sysc";
947 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
951 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
954 clock-names = "fck", "dss_clk";
955 #address-cells = <1>;
956 #size-cells = <1>;
960 compatible = "ti,dra7-hdmi";
965 reg-names = "wp", "pll", "phy", "core";
970 clock-names = "fck", "sys_clk";
972 dma-names = "audio_tx";
978 target-module@59000000 {
979 compatible = "ti,sysc-omap4", "ti,sysc";
981 reg-names = "rev";
983 clock-names = "fck";
984 #address-cells = <1>;
985 #size-cells = <1>;
993 clock-names = "core";
997 aes1_target: target-module@4b500000 {
998 compatible = "ti,sysc-omap2", "ti,sysc";
1002 reg-names = "rev", "sysc", "syss";
1003 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1005 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1009 ti,syss-mask = <1>;
1012 clock-names = "fck";
1013 #address-cells = <1>;
1014 #size-cells = <1>;
1018 compatible = "ti,omap4-aes";
1022 dma-names = "tx", "rx";
1024 clock-names = "fck";
1028 aes2_target: target-module@4b700000 {
1029 compatible = "ti,sysc-omap2", "ti,sysc";
1033 reg-names = "rev", "sysc", "syss";
1034 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1036 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1040 ti,syss-mask = <1>;
1043 clock-names = "fck";
1044 #address-cells = <1>;
1045 #size-cells = <1>;
1049 compatible = "ti,omap4-aes";
1053 dma-names = "tx", "rx";
1055 clock-names = "fck";
1059 sham1_target: target-module@4b101000 {
1060 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1064 reg-names = "rev", "sysc", "syss";
1065 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1067 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1070 ti,syss-mask = <1>;
1073 clock-names = "fck";
1074 #address-cells = <1>;
1075 #size-cells = <1>;
1079 compatible = "ti,omap5-sham";
1083 dma-names = "rx";
1085 clock-names = "fck";
1089 sham2_target: target-module@42701000 {
1090 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1094 reg-names = "rev", "sysc", "syss";
1095 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1097 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1100 ti,syss-mask = <1>;
1103 clock-names = "fck";
1104 #address-cells = <1>;
1105 #size-cells = <1>;
1109 compatible = "ti,omap5-sham";
1113 dma-names = "rx";
1115 clock-names = "fck";
1119 iva_hd_target: target-module@5a000000 {
1120 compatible = "ti,sysc-omap4", "ti,sysc";
1123 reg-names = "rev", "sysc";
1124 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1127 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1130 power-domains = <&prm_iva>;
1132 reset-names = "rstctrl";
1134 clock-names = "fck";
1135 #address-cells = <1>;
1136 #size-cells = <1>;
1145 opp_supply_mpu: opp-supply@4a003b20 {
1146 compatible = "ti,omap5-opp-supply";
1148 ti,efuse-settings = <
1154 ti,absolute-max-voltage-uv = <1500000>;
1159 thermal_zones: thermal-zones {
1160 #include "omap4-cpu-thermal.dtsi"
1161 #include "omap5-gpu-thermal.dtsi"
1162 #include "omap5-core-thermal.dtsi"
1163 #include "dra7-dspeve-thermal.dtsi"
1164 #include "dra7-iva-thermal.dtsi"
1170 polling-delay = <500>; /* milliseconds */
1210 #include "dra7-l4.dtsi"
1211 #include "dra7xx-clocks.dtsi"
1215 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1217 #power-domain-cells = <0>;
1221 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1223 #reset-cells = <1>;
1224 #power-domain-cells = <0>;
1228 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1230 #reset-cells = <1>;
1231 #power-domain-cells = <0>;
1235 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1237 #power-domain-cells = <0>;
1241 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1243 #reset-cells = <1>;
1244 #power-domain-cells = <0>;
1248 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1250 #reset-cells = <1>;
1251 #power-domain-cells = <0>;
1255 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1257 #power-domain-cells = <0>;
1261 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1263 #power-domain-cells = <0>;
1267 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1269 #power-domain-cells = <0>;
1273 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1275 #reset-cells = <1>;
1276 #power-domain-cells = <0>;
1280 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1282 #power-domain-cells = <0>;
1286 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1288 #power-domain-cells = <0>;
1292 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1294 #power-domain-cells = <0>;
1298 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1300 #reset-cells = <1>;
1301 #power-domain-cells = <0>;
1305 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1307 #power-domain-cells = <0>;
1311 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1313 #power-domain-cells = <0>;
1317 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1319 #power-domain-cells = <0>;
1323 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1325 #power-domain-cells = <0>;
1329 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1331 #power-domain-cells = <0>;
1335 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1337 #power-domain-cells = <0>;
1341 /* Preferred always-on timer for clockevent */
1343 ti,no-reset-on-init;
1344 ti,no-idle;
1346 assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
1347 assigned-clock-parents = <&sys_32k_ck>;
1353 ti,no-reset-on-init;
1354 ti,no-idle;
1356 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
1357 assigned-clock-parents = <&timer_sys_clk_div>;
1362 ti,no-reset-on-init;
1363 ti,no-idle;
1365 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
1366 assigned-clock-parents = <&timer_sys_clk_div>;