Lines Matching +full:omap4 +full:- +full:aes
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 * Based on "omap4.dtsi"
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
20 interrupt-parent = <&crossbar_mpu>;
47 compatible = "arm,armv7-timer";
53 interrupt-parent = <&gic>;
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
58 interrupt-controller;
59 #interrupt-cells = <3>;
65 interrupt-parent = <&gic>;
68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 interrupt-controller;
71 #interrupt-cells = <3>;
73 interrupt-parent = <&gic>;
77 #address-cells = <1>;
78 #size-cells = <0>;
82 compatible = "arm,cortex-a15";
85 operating-points-v2 = <&cpu0_opp_table>;
88 clock-names = "cpu";
90 clock-latency = <300000>; /* From omap-cpufreq driver */
93 #cooling-cells = <2>; /* min followed by max */
95 vbb-supply = <&abb_mpu>;
99 cpu0_opp_table: opp-table {
100 compatible = "operating-points-v2-ti-cpu";
103 opp-1000000000 {
105 opp-hz = /bits/ 64 <1000000000>;
106 opp-microvolt = <1060000 850000 1150000>,
108 opp-supported-hw = <0xFF 0x01>;
109 opp-suspend;
112 opp-1176000000 {
114 opp-hz = /bits/ 64 <1176000000>;
115 opp-microvolt = <1160000 885000 1160000>,
118 opp-supported-hw = <0xFF 0x02>;
121 opp-1500000000 {
123 opp-hz = /bits/ 64 <1500000000>;
124 opp-microvolt = <1210000 950000 1250000>,
126 opp-supported-hw = <0xFF 0x04>;
138 compatible = "simple-pm-bus";
139 power-domains = <&prm_core>;
142 #address-cells = <1>;
143 #size-cells = <1>;
145 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
147 l3-noc@44000000 {
148 compatible = "ti,dra7-l3-noc";
151 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
162 target-module@48210000 {
163 compatible = "ti,sysc-omap4-simple", "ti,sysc";
164 power-domains = <&prm_mpu>;
166 clock-names = "fck";
167 #address-cells = <1>;
168 #size-cells = <1>;
172 compatible = "ti,omap5-mpu";
184 * 26-678. Main Sequence PCIe Controller Global Initialization"
187 axi0: target-module@51000000 {
188 compatible = "ti,sysc-omap4", "ti,sysc";
189 power-domains = <&prm_l3init>;
191 reset-names = "rstctrl";
195 clock-names = "fck", "phy-clk", "phy-clk-div";
196 #size-cells = <1>;
197 #address-cells = <1>;
200 dma-ranges;
207 reg-names = "rc_dbics", "ti_conf", "config";
209 #address-cells = <3>;
210 #size-cells = <2>;
214 bus-range = <0x00 0xff>;
215 #interrupt-cells = <1>;
216 num-lanes = <1>;
217 linux,pci-domain = <0>;
219 phy-names = "pcie-phy0";
220 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
221 interrupt-map-mask = <0 0 0 7>;
222 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
226 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
228 pcie1_intc: interrupt-controller {
229 interrupt-controller;
230 #address-cells = <0>;
231 #interrupt-cells = <1>;
237 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
239 num-lanes = <1>;
240 num-ib-windows = <4>;
241 num-ob-windows = <16>;
243 phy-names = "pcie-phy0";
244 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
245 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
253 * 26-678. Main Sequence PCIe Controller Global Initialization"
256 axi1: target-module@51800000 {
257 compatible = "ti,sysc-omap4", "ti,sysc";
261 clock-names = "fck", "phy-clk", "phy-clk-div";
262 power-domains = <&prm_l3init>;
264 reset-names = "rstctrl";
265 #size-cells = <1>;
266 #address-cells = <1>;
269 dma-ranges;
273 reg-names = "rc_dbics", "ti_conf", "config";
275 #address-cells = <3>;
276 #size-cells = <2>;
280 bus-range = <0x00 0xff>;
281 #interrupt-cells = <1>;
282 num-lanes = <1>;
283 linux,pci-domain = <1>;
285 phy-names = "pcie-phy0";
286 interrupt-map-mask = <0 0 0 7>;
287 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
291 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
292 pcie2_intc: interrupt-controller {
293 interrupt-controller;
294 #address-cells = <0>;
295 #interrupt-cells = <1>;
301 compatible = "mmio-sram";
304 #address-cells = <1>;
305 #size-cells = <1>;
317 sram-hs@0 {
318 compatible = "ti,secure-ram";
331 compatible = "mmio-sram";
334 #address-cells = <1>;
335 #size-cells = <1>;
340 compatible = "mmio-sram";
343 #address-cells = <1>;
344 #size-cells = <1>;
354 compatible = "ti,dra752-bandgap";
356 #thermal-sensor-cells = <1>;
365 compatible = "ti,dra7-iodelay";
367 #address-cells = <1>;
368 #size-cells = <0>;
369 #pinctrl-cells = <2>;
372 target-module@43300000 {
373 compatible = "ti,sysc-omap4", "ti,sysc";
376 reg-names = "rev", "sysc";
377 ti,sysc-midle = <SYSC_IDLE_FORCE>,
380 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
384 clock-names = "fck";
385 #address-cells = <1>;
386 #size-cells = <1>;
390 compatible = "ti,edma3-tpcc";
392 reg-names = "edma3_cc";
396 interrupt-names = "edma3_ccint", "edma3_mperr",
398 dma-requests = <64>;
399 #dma-cells = <2>;
405 * ti,edma-memcpy-channels = <20 21>;
412 target-module@43400000 {
413 compatible = "ti,sysc-omap4", "ti,sysc";
416 reg-names = "rev", "sysc";
417 ti,sysc-midle = <SYSC_IDLE_FORCE>,
420 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
424 clock-names = "fck";
425 #address-cells = <1>;
426 #size-cells = <1>;
430 compatible = "ti,edma3-tptc";
433 interrupt-names = "edma3_tcerrint";
437 target-module@43500000 {
438 compatible = "ti,sysc-omap4", "ti,sysc";
441 reg-names = "rev", "sysc";
442 ti,sysc-midle = <SYSC_IDLE_FORCE>,
445 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
449 clock-names = "fck";
450 #address-cells = <1>;
451 #size-cells = <1>;
455 compatible = "ti,edma3-tptc";
458 interrupt-names = "edma3_tcerrint";
462 target-module@4e000000 {
463 compatible = "ti,sysc-omap2", "ti,sysc";
466 reg-names = "rev", "sysc";
467 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
471 #size-cells = <1>;
472 #address-cells = <1>;
475 compatible = "ti,omap5-dmm";
482 compatible = "ti,dra7-ipu";
484 reg-names = "l2ram";
489 firmware-name = "dra7-ipu1-fw.xem4";
493 compatible = "ti,dra7-ipu";
495 reg-names = "l2ram";
500 firmware-name = "dra7-ipu2-fw.xem4";
504 compatible = "ti,dra7-dsp";
508 reg-names = "l2ram", "l1pram", "l1dram";
514 firmware-name = "dra7-dsp1-fw.xe66";
517 target-module@40d01000 {
518 compatible = "ti,sysc-omap2", "ti,sysc";
522 reg-names = "rev", "sysc", "syss";
523 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
526 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
530 clock-names = "fck";
532 reset-names = "rstctrl";
534 #size-cells = <1>;
535 #address-cells = <1>;
538 compatible = "ti,dra7-dsp-iommu";
541 #iommu-cells = <0>;
542 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
546 target-module@40d02000 {
547 compatible = "ti,sysc-omap2", "ti,sysc";
551 reg-names = "rev", "sysc", "syss";
552 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
555 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
559 clock-names = "fck";
561 reset-names = "rstctrl";
563 #size-cells = <1>;
564 #address-cells = <1>;
567 compatible = "ti,dra7-dsp-iommu";
570 #iommu-cells = <0>;
571 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
575 target-module@58882000 {
576 compatible = "ti,sysc-omap2", "ti,sysc";
580 reg-names = "rev", "sysc", "syss";
581 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
584 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
588 clock-names = "fck";
590 reset-names = "rstctrl";
591 #address-cells = <1>;
592 #size-cells = <1>;
596 compatible = "ti,dra7-iommu";
599 #iommu-cells = <0>;
600 ti,iommu-bus-err-back;
604 target-module@55082000 {
605 compatible = "ti,sysc-omap2", "ti,sysc";
609 reg-names = "rev", "sysc", "syss";
610 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
613 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
617 clock-names = "fck";
619 reset-names = "rstctrl";
620 #address-cells = <1>;
621 #size-cells = <1>;
625 compatible = "ti,dra7-iommu";
628 #iommu-cells = <0>;
629 ti,iommu-bus-err-back;
633 abb_mpu: regulator-abb-mpu@4ae07ddc {
634 compatible = "ti,abb-v3";
635 regulator-name = "abb_mpu";
636 #address-cells = <0>;
637 #size-cells = <0>;
639 ti,settling-time = <50>;
640 ti,clock-cycles = <16>;
645 reg-names = "setup-address", "control-address",
646 "int-address", "efuse-address",
647 "ldo-address";
648 ti,tranxdone-status-mask = <0x80>;
650 ti,ldovbb-override-mask = <0x400>;
652 ti,ldovbb-vset-mask = <0x1F>;
666 abb_ivahd: regulator-abb-ivahd@4ae07e34 {
667 compatible = "ti,abb-v3";
668 regulator-name = "abb_ivahd";
669 #address-cells = <0>;
670 #size-cells = <0>;
672 ti,settling-time = <50>;
673 ti,clock-cycles = <16>;
678 reg-names = "setup-address", "control-address",
679 "int-address", "efuse-address",
680 "ldo-address";
681 ti,tranxdone-status-mask = <0x40000000>;
683 ti,ldovbb-override-mask = <0x400>;
685 ti,ldovbb-vset-mask = <0x1F>;
699 abb_dspeve: regulator-abb-dspeve@4ae07e30 {
700 compatible = "ti,abb-v3";
701 regulator-name = "abb_dspeve";
702 #address-cells = <0>;
703 #size-cells = <0>;
705 ti,settling-time = <50>;
706 ti,clock-cycles = <16>;
711 reg-names = "setup-address", "control-address",
712 "int-address", "efuse-address",
713 "ldo-address";
714 ti,tranxdone-status-mask = <0x20000000>;
716 ti,ldovbb-override-mask = <0x400>;
718 ti,ldovbb-vset-mask = <0x1F>;
732 abb_gpu: regulator-abb-gpu@4ae07de4 {
733 compatible = "ti,abb-v3";
734 regulator-name = "abb_gpu";
735 #address-cells = <0>;
736 #size-cells = <0>;
738 ti,settling-time = <50>;
739 ti,clock-cycles = <16>;
744 reg-names = "setup-address", "control-address",
745 "int-address", "efuse-address",
746 "ldo-address";
747 ti,tranxdone-status-mask = <0x10000000>;
749 ti,ldovbb-override-mask = <0x400>;
751 ti,ldovbb-vset-mask = <0x1F>;
765 target-module@4b300000 {
766 compatible = "ti,sysc-omap4", "ti,sysc";
769 reg-names = "rev", "sysc";
770 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
775 clock-names = "fck";
776 #address-cells = <1>;
777 #size-cells = <1>;
782 compatible = "ti,dra7xxx-qspi";
785 reg-names = "qspi_base", "qspi_mmap";
786 syscon-chipselects = <&scm_conf 0x558>;
787 #address-cells = <1>;
788 #size-cells = <0>;
790 clock-names = "fck";
791 num-cs = <4>;
800 target-module@50000000 {
801 compatible = "ti,sysc-omap2", "ti,sysc";
805 reg-names = "rev", "sysc", "syss";
806 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
809 ti,syss-mask = <1>;
811 clock-names = "fck";
812 #address-cells = <1>;
813 #size-cells = <1>;
818 compatible = "ti,am3352-gpmc";
822 dma-names = "rxtx";
823 gpmc,num-cs = <8>;
824 gpmc,num-waitpins = <2>;
825 #address-cells = <2>;
826 #size-cells = <1>;
827 interrupt-controller;
828 #interrupt-cells = <2>;
829 gpio-controller;
830 #gpio-cells = <2>;
835 target-module@56000000 {
836 compatible = "ti,sysc-omap4", "ti,sysc";
839 reg-names = "rev", "sysc";
840 ti,sysc-midle = <SYSC_IDLE_FORCE>,
843 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
848 clock-names = "fck";
849 #address-cells = <1>;
850 #size-cells = <1>;
854 compatible = "ti,am5728-gpu", "img,powervr-sgx544";
861 compatible = "ti,irq-crossbar";
863 interrupt-controller;
864 interrupt-parent = <&wakeupgen>;
865 #interrupt-cells = <3>;
866 ti,max-irqs = <160>;
867 ti,max-crossbar-sources = <MAX_SOURCES>;
868 ti,reg-size = <2>;
869 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
870 ti,irqs-skip = <10 133 139 140>;
871 ti,irqs-safe-map = <0>;
874 target-module@58000000 {
875 compatible = "ti,sysc-omap2", "ti,sysc";
878 reg-names = "rev", "syss";
879 ti,syss-mask = <1>;
884 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
885 #address-cells = <1>;
886 #size-cells = <1>;
890 compatible = "ti,dra7-dss";
895 syscon-pll-ctrl = <&scm_conf 0x538>;
896 #address-cells = <1>;
897 #size-cells = <1>;
900 target-module@1000 {
901 compatible = "ti,sysc-omap2", "ti,sysc";
905 reg-names = "rev", "sysc", "syss";
906 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
909 ti,sysc-midle = <SYSC_IDLE_FORCE>,
912 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
916 ti,syss-mask = <1>;
918 clock-names = "fck";
919 #address-cells = <1>;
920 #size-cells = <1>;
924 compatible = "ti,dra7-dispc";
928 clock-names = "fck";
930 syscon-pol = <&scm_conf 0x534>;
934 target-module@40000 {
935 compatible = "ti,sysc-omap4", "ti,sysc";
938 reg-names = "rev", "sysc";
939 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
943 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
946 clock-names = "fck", "dss_clk";
947 #address-cells = <1>;
948 #size-cells = <1>;
952 compatible = "ti,dra7-hdmi";
957 reg-names = "wp", "pll", "phy", "core";
962 clock-names = "fck", "sys_clk";
964 dma-names = "audio_tx";
970 target-module@59000000 {
971 compatible = "ti,sysc-omap4", "ti,sysc";
973 reg-names = "rev";
975 clock-names = "fck";
976 #address-cells = <1>;
977 #size-cells = <1>;
985 clock-names = "core";
989 aes1_target: target-module@4b500000 {
990 compatible = "ti,sysc-omap2", "ti,sysc";
994 reg-names = "rev", "sysc", "syss";
995 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
997 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1001 ti,syss-mask = <1>;
1004 clock-names = "fck";
1005 #address-cells = <1>;
1006 #size-cells = <1>;
1009 aes1: aes@0 {
1010 compatible = "ti,omap4-aes";
1014 dma-names = "tx", "rx";
1016 clock-names = "fck";
1020 aes2_target: target-module@4b700000 {
1021 compatible = "ti,sysc-omap2", "ti,sysc";
1025 reg-names = "rev", "sysc", "syss";
1026 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1028 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1032 ti,syss-mask = <1>;
1035 clock-names = "fck";
1036 #address-cells = <1>;
1037 #size-cells = <1>;
1040 aes2: aes@0 {
1041 compatible = "ti,omap4-aes";
1045 dma-names = "tx", "rx";
1047 clock-names = "fck";
1051 sham1_target: target-module@4b101000 {
1052 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1056 reg-names = "rev", "sysc", "syss";
1057 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1059 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1062 ti,syss-mask = <1>;
1065 clock-names = "fck";
1066 #address-cells = <1>;
1067 #size-cells = <1>;
1071 compatible = "ti,omap5-sham";
1075 dma-names = "rx";
1077 clock-names = "fck";
1081 sham2_target: target-module@42701000 {
1082 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1086 reg-names = "rev", "sysc", "syss";
1087 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1089 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1092 ti,syss-mask = <1>;
1095 clock-names = "fck";
1096 #address-cells = <1>;
1097 #size-cells = <1>;
1101 compatible = "ti,omap5-sham";
1105 dma-names = "rx";
1107 clock-names = "fck";
1111 iva_hd_target: target-module@5a000000 {
1112 compatible = "ti,sysc-omap4", "ti,sysc";
1115 reg-names = "rev", "sysc";
1116 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1119 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1122 power-domains = <&prm_iva>;
1124 reset-names = "rstctrl";
1126 clock-names = "fck";
1127 #address-cells = <1>;
1128 #size-cells = <1>;
1137 opp_supply_mpu: opp-supply@4a003b20 {
1138 compatible = "ti,omap5-opp-supply";
1140 ti,efuse-settings = <
1146 ti,absolute-max-voltage-uv = <1500000>;
1151 thermal_zones: thermal-zones {
1152 #include "omap4-cpu-thermal.dtsi"
1153 #include "omap5-gpu-thermal.dtsi"
1154 #include "omap5-core-thermal.dtsi"
1155 #include "dra7-dspeve-thermal.dtsi"
1156 #include "dra7-iva-thermal.dtsi"
1162 polling-delay = <500>; /* milliseconds */
1202 #include "dra7-l4.dtsi"
1203 #include "dra7xx-clocks.dtsi"
1207 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1209 #power-domain-cells = <0>;
1213 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1215 #reset-cells = <1>;
1216 #power-domain-cells = <0>;
1220 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1222 #reset-cells = <1>;
1223 #power-domain-cells = <0>;
1227 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1229 #power-domain-cells = <0>;
1233 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1235 #reset-cells = <1>;
1236 #power-domain-cells = <0>;
1240 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1242 #reset-cells = <1>;
1243 #power-domain-cells = <0>;
1247 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1249 #power-domain-cells = <0>;
1253 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1255 #power-domain-cells = <0>;
1259 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1261 #power-domain-cells = <0>;
1265 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1267 #reset-cells = <1>;
1268 #power-domain-cells = <0>;
1272 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1274 #power-domain-cells = <0>;
1278 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1280 #power-domain-cells = <0>;
1284 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1286 #power-domain-cells = <0>;
1290 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1292 #reset-cells = <1>;
1293 #power-domain-cells = <0>;
1297 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1299 #power-domain-cells = <0>;
1303 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1305 #power-domain-cells = <0>;
1309 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1311 #power-domain-cells = <0>;
1315 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1317 #power-domain-cells = <0>;
1321 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1323 #power-domain-cells = <0>;
1327 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1329 #power-domain-cells = <0>;
1333 /* Preferred always-on timer for clockevent */
1335 ti,no-reset-on-init;
1336 ti,no-idle;
1338 assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
1339 assigned-clock-parents = <&sys_32k_ck>;
1345 ti,no-reset-on-init;
1346 ti,no-idle;
1348 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
1349 assigned-clock-parents = <&timer_sys_clk_div>;
1354 ti,no-reset-on-init;
1355 ti,no-idle;
1357 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
1358 assigned-clock-parents = <&timer_sys_clk_div>;