Lines Matching full:l4per2_clkctrl
2309 clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>;
2420 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2450 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2480 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2550 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2596 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2642 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2795 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2796 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2797 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2814 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2816 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2831 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2832 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2849 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2850 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2865 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2866 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2883 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2884 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2899 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2900 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2917 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2918 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2933 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2934 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2951 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2952 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2967 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2968 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2985 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2986 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
3001 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
3002 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
3019 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
3020 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
3030 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;