Lines Matching +full:0 +full:x4c000
31 #size-cells = <0>;
32 cpu@0 {
35 reg = <0>;
65 reg = <0x47400000 0x1000>;
73 reg = <0x47401300 0x100>;
76 #phy-cells = <0>;
81 reg = <0x47401400 0x400
82 0x47401000 0x200>;
94 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
95 &cppi41dma 2 0 &cppi41dma 3 0
96 &cppi41dma 4 0 &cppi41dma 5 0
97 &cppi41dma 6 0 &cppi41dma 7 0
98 &cppi41dma 8 0 &cppi41dma 9 0
99 &cppi41dma 10 0 &cppi41dma 11 0
100 &cppi41dma 12 0 &cppi41dma 13 0
101 &cppi41dma 14 0 &cppi41dma 0 1
120 reg = <0x47401c00 0x400
121 0x47401800 0x200>;
132 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
133 &cppi41dma 17 0 &cppi41dma 18 0
134 &cppi41dma 19 0 &cppi41dma 20 0
135 &cppi41dma 21 0 &cppi41dma 22 0
136 &cppi41dma 23 0 &cppi41dma 24 0
137 &cppi41dma 25 0 &cppi41dma 26 0
138 &cppi41dma 27 0 &cppi41dma 28 0
139 &cppi41dma 29 0 &cppi41dma 15 1
158 reg = <0x47400000 0x1000
159 0x47402000 0x1000
160 0x47403000 0x1000
161 0x47404000 0x4000>;
177 * actual device is typically 0x1000 before the target agent
178 * except in cases where the module is larger than 0x1000.
184 ranges = <0 0x48000000 0x2000000>;
189 #size-cells = <0>;
191 reg = <0x28000 0x1000>;
198 reg = <0x80000 0x2000>;
206 reg = <0x32000 0x2000>;
218 reg = <0x4c000 0x2000>;
230 reg = <0x1ac000 0x2000>;
242 reg = <0x1ae000 0x2000>;
253 #size-cells = <0>;
255 reg = <0x2a000 0x1000>;
261 reg = <0x30000 0x1000>;
263 #size-cells = <0>;
267 dmas = <&edma 16 0 &edma 17 0
268 &edma 18 0 &edma 19 0
269 &edma 20 0 &edma 21 0
270 &edma 22 0 &edma 23 0>;
278 reg = <0x1a0000 0x1000>;
280 #size-cells = <0>;
284 dmas = <&edma 42 0 &edma 43 0
285 &edma 44 0 &edma 45 0>;
292 reg = <0x1a2000 0x1000>;
294 #size-cells = <0>;
302 reg = <0x1a4000 0x1000>;
304 #size-cells = <0>;
312 reg = <0x2e000 0x4>,
313 <0x2e010 0x4>;
324 ranges = <0x0 0x2e000 0x1000>;
326 timer1: timer@0 {
328 reg = <0x0 0x400>;
339 reg = <0x20000 0x2000>;
342 dmas = <&edma 26 0 &edma 27 0>;
349 reg = <0x22000 0x2000>;
352 dmas = <&edma 28 0 &edma 29 0>;
359 reg = <0x24000 0x2000>;
362 dmas = <&edma 30 0 &edma 31 0>;
368 reg = <0x40000 0x4>,
369 <0x40010 0x4>;
380 ranges = <0x0 0x40000 0x1000>;
382 timer2: timer@0 {
384 reg = <0 0x1000>;
393 reg = <0x42000 0x2000>;
401 dmas = <&edma 24 0
402 &edma 25 0>;
406 reg = <0x60000 0x1000>;
411 reg = <0xc0000 0x1000>;
419 dmas = <&edma 2 0
420 &edma 3 0>;
424 reg = <0x1d8000 0x1000>;
429 reg = <0x140000 0x20000>;
432 ranges = <0 0x140000 0x20000>;
434 scm_conf: scm_conf@0 {
436 reg = <0x0 0x800>;
439 ranges = <0 0 0x800>;
443 reg = <0x650 0x4>;
449 #size-cells = <0>;
458 reg = <0x620 0x10
459 0x648 0x4>;
465 reg = <0xf90 0x40>;
481 reg = <0x800 0x438>;
483 #size-cells = <0>;
486 pinctrl-single,function-mask = <0x307ff>;
491 reg = <0x1b00 0x100>;
494 #phy-cells = <0>;
500 reg = <0x180000 0x2000>;
503 ranges = <0 0x180000 0x2000>;
507 #size-cells = <0>;
517 reg = <0x1c5000 0x1000>;
520 ranges = <0 0x1c5000 0x1000>;
524 #size-cells = <0>;
534 reg = <0x1c7000 0x1000>;
543 reg = <0x48200000 0x1000>;
552 reg = <0x47810000 0x1000>;
557 reg = <0x49000000 0x4>;
559 clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>;
563 ranges = <0x0 0x49000000 0x10000>;
565 edma: dma@0 {
567 reg = <0 0x10000>;
576 <&edma_tptc2 3>, <&edma_tptc3 0>;
584 reg = <0x49800000 0x4>,
585 <0x49800010 0x4>;
591 clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>;
595 ranges = <0x0 0x49800000 0x100000>;
597 edma_tptc0: dma@0 {
599 reg = <0 0x100000>;
607 reg = <0x49900000 0x4>,
608 <0x49900010 0x4>;
614 clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>;
618 ranges = <0x0 0x49900000 0x100000>;
620 edma_tptc1: dma@0 {
622 reg = <0 0x100000>;
630 reg = <0x49a00000 0x4>,
631 <0x49a00010 0x4>;
637 clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>;
641 ranges = <0x0 0x49a00000 0x100000>;
643 edma_tptc2: dma@0 {
645 reg = <0 0x100000>;
653 reg = <0x49b00000 0x4>,
654 <0x49b00010 0x4>;
660 clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>;
664 ranges = <0x0 0x49b00000 0x100000>;
666 edma_tptc3: dma@0 {
668 reg = <0 0x100000>;
679 ranges = <0 0x4a000000 0x1b4040>;
683 reg = <0x100900 0x4>,
684 <0x100908 0x4>,
685 <0x100904 0x4>;
687 ti,sysc-mask = <0>;
693 clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
697 ranges = <0 0x100000 0x8000>;
699 mac: ethernet@0 {
705 bd_ram_size = <0x2000>;
706 mac_control = <0x20>;
708 active_slave = <0>;
709 cpts_clock_mult = <0x80000000>;
711 reg = <0 0x800>,
712 <0x900 0x100>;
722 ranges = <0 0 0x8000>;
730 #size-cells = <0>;
732 reg = <0x800 0x100>;
754 reg = <0x50000000 0x2000>;
774 timer@0 {
784 timer@0 {