Lines Matching +full:0 +full:x00280000
1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
22 <0x00000800 0x00000800 0x000800>, /* ap 1 */
23 <0x00001000 0x00001000 0x000400>, /* ap 2 */
24 <0x00001400 0x00001400 0x000400>; /* ap 3 */
27 segment@100000 { /* 0x44d00000 */
31 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
32 <0x00004000 0x00104000 0x001000>, /* ap 5 */
33 <0x00080000 0x00180000 0x002000>, /* ap 6 */
34 <0x00082000 0x00182000 0x001000>, /* ap 7 */
35 <0x000f0000 0x001f0000 0x010000>; /* ap 8 */
37 target-module@0 { /* 0x44d00000, ap 4 28.0 */
39 reg = <0x0 0x4>;
41 clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>;
45 ranges = <0x00000000 0x00000000 0x4000>,
46 <0x00080000 0x00080000 0x2000>;
48 wkup_m3: cpu@0 {
50 reg = <0x00000000 0x4000>,
51 <0x00080000 0x2000>;
59 target-module@f0000 { /* 0x44df0000, ap 8 58.0 */
61 reg = <0xf0000 0x4>;
65 ranges = <0x0 0xf0000 0x10000>;
67 prcm: prcm@0 {
69 reg = <0x0 0x11000>;
73 ranges = <0 0 0x11000>;
77 #size-cells = <0>;
86 segment@200000 { /* 0x44e00000 */
90 ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */
91 <0x00003000 0x00203000 0x001000>, /* ap 10 */
92 <0x00004000 0x00204000 0x001000>, /* ap 11 */
93 <0x00005000 0x00205000 0x001000>, /* ap 12 */
94 <0x00006000 0x00206000 0x001000>, /* ap 13 */
95 <0x00007000 0x00207000 0x001000>, /* ap 14 */
96 <0x00008000 0x00208000 0x001000>, /* ap 15 */
97 <0x00009000 0x00209000 0x001000>, /* ap 16 */
98 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */
99 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */
100 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */
101 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */
102 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */
103 <0x00010000 0x00210000 0x010000>, /* ap 22 */
104 <0x00030000 0x00230000 0x001000>, /* ap 23 */
105 <0x00031000 0x00231000 0x001000>, /* ap 24 */
106 <0x00032000 0x00232000 0x001000>, /* ap 25 */
107 <0x00033000 0x00233000 0x001000>, /* ap 26 */
108 <0x00034000 0x00234000 0x001000>, /* ap 27 */
109 <0x00035000 0x00235000 0x001000>, /* ap 28 */
110 <0x00036000 0x00236000 0x001000>, /* ap 29 */
111 <0x00037000 0x00237000 0x001000>, /* ap 30 */
112 <0x00038000 0x00238000 0x001000>, /* ap 31 */
113 <0x00039000 0x00239000 0x001000>, /* ap 32 */
114 <0x0003a000 0x0023a000 0x001000>, /* ap 33 */
115 <0x0003e000 0x0023e000 0x001000>, /* ap 34 */
116 <0x0003f000 0x0023f000 0x001000>, /* ap 35 */
117 <0x00040000 0x00240000 0x040000>, /* ap 36 */
118 <0x00080000 0x00280000 0x001000>, /* ap 37 */
119 <0x00088000 0x00288000 0x008000>, /* ap 38 */
120 <0x00092000 0x00292000 0x001000>, /* ap 39 */
121 <0x00086000 0x00286000 0x001000>, /* ap 40 */
122 <0x00087000 0x00287000 0x001000>, /* ap 41 */
123 <0x00090000 0x00290000 0x001000>, /* ap 42 */
124 <0x00091000 0x00291000 0x001000>; /* ap 43 */
126 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */
131 ranges = <0x0 0x3000 0x1000>;
134 target-module@5000 { /* 0x44e05000, ap 12 30.0 */
139 ranges = <0x0 0x5000 0x1000>;
142 target-module@7000 { /* 0x44e07000, ap 14 20.0 */
144 reg = <0x7000 0x4>,
145 <0x7010 0x4>,
146 <0x7114 0x4>;
157 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 0>,
162 ranges = <0x0 0x7000 0x1000>;
164 gpio0: gpio@0 {
166 reg = <0x0 0x1000>;
176 target-module@9000 { /* 0x44e09000, ap 16 04.0 */
178 reg = <0x9050 0x4>,
179 <0x9054 0x4>,
180 <0x9058 0x4>;
190 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_UART1_CLKCTRL 0>;
194 ranges = <0x0 0x9000 0x1000>;
196 uart0: serial@0 {
198 reg = <0x0 0x2000>;
203 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
205 reg = <0xb000 0x8>,
206 <0xb010 0x8>,
207 <0xb090 0x8>;
219 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_I2C1_CLKCTRL 0>;
223 ranges = <0x0 0xb000 0x1000>;
225 i2c0: i2c@0 {
227 reg = <0x0 0x1000>;
230 #size-cells = <0>;
235 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
237 reg = <0xd000 0x4>,
238 <0xd010 0x4>;
245 clocks = <&l3s_tsc_clkctrl AM4_L3S_TSC_ADC_TSC_CLKCTRL 0>;
249 ranges = <0x0 0xd000 0x1000>;
251 tscadc: tscadc@0 {
253 reg = <0x0 0x1000>;
258 dmas = <&edma 53 0>, <&edma 57 0>;
273 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
275 reg = <0x10000 0x4>;
277 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_CONTROL_CLKCTRL 0>;
282 ranges = <0x0 0x10000 0x10000>;
284 scm: scm@0 {
286 reg = <0x0 0x4000>;
289 ranges = <0 0 0x4000>;
294 reg = <0x800 0x31c>;
296 #size-cells = <0>;
301 pinctrl-single,function-mask = <0xffffffff>;
304 scm_conf: scm_conf@0 {
306 reg = <0x0 0x800>;
312 reg = <0x650 0x4>;
318 #size-cells = <0>;
324 reg = <0x1324 0x44>;
332 reg = <0xf90 0x40>;
343 timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */
345 reg = <0x31000 0x4>,
346 <0x31010 0x4>,
347 <0x31014 0x4>;
357 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>;
361 ranges = <0x0 0x31000 0x1000>;
363 timer1: timer@0 {
365 reg = <0x0 0x400>;
373 target-module@33000 { /* 0x44e33000, ap 26 18.0 */
378 ranges = <0x0 0x33000 0x1000>;
381 target-module@35000 { /* 0x44e35000, ap 28 50.0 */
383 reg = <0x35000 0x4>,
384 <0x35010 0x4>,
385 <0x35014 0x4>;
395 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
399 ranges = <0x0 0x35000 0x1000>;
401 wdt: wdt@0 {
403 reg = <0x0 0x1000>;
408 target-module@37000 { /* 0x44e37000, ap 30 08.0 */
413 ranges = <0x0 0x37000 0x1000>;
416 target-module@39000 { /* 0x44e39000, ap 32 02.0 */
421 ranges = <0x0 0x39000 0x1000>;
424 rtc_target: target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */
426 reg = <0x3e074 0x4>,
427 <0x3e078 0x4>;
435 clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>;
439 ranges = <0x0 0x3e000 0x1000>;
441 rtc: rtc@0 {
444 reg = <0x0 0x1000>;
454 target-module@40000 { /* 0x44e40000, ap 36 68.0 */
459 ranges = <0x0 0x40000 0x40000>;
462 target-module@86000 { /* 0x44e86000, ap 40 70.0 */
464 reg = <0x86000 0x4>,
465 <0x86004 0x4>;
470 clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL 0>;
474 ranges = <0x0 0x86000 0x1000>;
476 counter32k: counter@0 {
478 reg = <0x0 0x40>;
482 target-module@88000 { /* 0x44e88000, ap 38 12.0 */
487 ranges = <0x00000000 0x00088000 0x00008000>,
488 <0x00008000 0x00090000 0x00001000>,
489 <0x00009000 0x00091000 0x00001000>;
494 &l4_fast { /* 0x4a000000 */
497 clocks = <&l3_clkctrl AM4_L3_L4_HS_CLKCTRL 0>;
499 reg = <0x4a000000 0x800>,
500 <0x4a000800 0x800>,
501 <0x4a001000 0x400>;
505 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
507 segment@0 { /* 0x4a000000 */
511 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
512 <0x00000800 0x00000800 0x000800>, /* ap 1 */
513 <0x00001000 0x00001000 0x000400>, /* ap 2 */
514 <0x00100000 0x00100000 0x008000>, /* ap 3 */
515 <0x00108000 0x00108000 0x001000>, /* ap 4 */
516 <0x00400000 0x00400000 0x002000>, /* ap 5 */
517 <0x00402000 0x00402000 0x001000>, /* ap 6 */
518 <0x00200000 0x00200000 0x080000>, /* ap 7 */
519 <0x00280000 0x00280000 0x001000>; /* ap 8 */
521 target-module@100000 { /* 0x4a100000, ap 3 04.0 */
523 reg = <0x101200 0x4>,
524 <0x101208 0x4>,
525 <0x101204 0x4>;
527 ti,sysc-mask = <0>;
533 clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
537 ranges = <0x0 0x100000 0x8000>;
539 mac_sw: switch@0 {
541 reg = <0x0 0x4000>;
542 ranges = <0 0 0x4000>;
560 #size-cells = <0>;
566 phys = <&phy_gmii_sel 1 0>;
573 phys = <&phy_gmii_sel 2 0>;
582 #size-cells = <0>;
584 reg = <0x1000 0x100>;
594 target-module@200000 { /* 0x4a200000, ap 7 02.0 */
599 ranges = <0x0 0x200000 0x80000>;
602 target-module@400000 { /* 0x4a400000, ap 5 08.0 */
607 ranges = <0x0 0x400000 0x2000>;
612 &l4_per { /* 0x48000000 */
615 clocks = <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
617 reg = <0x48000000 0x800>,
618 <0x48000800 0x800>,
619 <0x48001000 0x400>,
620 <0x48001400 0x400>,
621 <0x48001800 0x400>,
622 <0x48001c00 0x400>;
626 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */
627 <0x00100000 0x48100000 0x100000>, /* segment 1 */
628 <0x00200000 0x48200000 0x100000>, /* segment 2 */
629 <0x00300000 0x48300000 0x100000>, /* segment 3 */
630 <0x46000000 0x46000000 0x400000>, /* l3 data port */
631 <0x46400000 0x46400000 0x400000>; /* l3 data port */
633 segment@0 { /* 0x48000000 */
637 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
638 <0x00000800 0x00000800 0x000800>, /* ap 1 */
639 <0x00001000 0x00001000 0x000400>, /* ap 2 */
640 <0x00001400 0x00001400 0x000400>, /* ap 3 */
641 <0x00001800 0x00001800 0x000400>, /* ap 4 */
642 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */
643 <0x00008000 0x00008000 0x001000>, /* ap 6 */
644 <0x00009000 0x00009000 0x001000>, /* ap 7 */
645 <0x00022000 0x00022000 0x001000>, /* ap 8 */
646 <0x00023000 0x00023000 0x001000>, /* ap 9 */
647 <0x00024000 0x00024000 0x001000>, /* ap 10 */
648 <0x00025000 0x00025000 0x001000>, /* ap 11 */
649 <0x0002a000 0x0002a000 0x001000>, /* ap 12 */
650 <0x0002b000 0x0002b000 0x001000>, /* ap 13 */
651 <0x00038000 0x00038000 0x002000>, /* ap 14 */
652 <0x0003a000 0x0003a000 0x001000>, /* ap 15 */
653 <0x0003c000 0x0003c000 0x002000>, /* ap 16 */
654 <0x0003e000 0x0003e000 0x001000>, /* ap 17 */
655 <0x00040000 0x00040000 0x001000>, /* ap 18 */
656 <0x00041000 0x00041000 0x001000>, /* ap 19 */
657 <0x00042000 0x00042000 0x001000>, /* ap 20 */
658 <0x00043000 0x00043000 0x001000>, /* ap 21 */
659 <0x00044000 0x00044000 0x001000>, /* ap 22 */
660 <0x00045000 0x00045000 0x001000>, /* ap 23 */
661 <0x00046000 0x00046000 0x001000>, /* ap 24 */
662 <0x00047000 0x00047000 0x001000>, /* ap 25 */
663 <0x00048000 0x00048000 0x001000>, /* ap 26 */
664 <0x00049000 0x00049000 0x001000>, /* ap 27 */
665 <0x0004c000 0x0004c000 0x001000>, /* ap 28 */
666 <0x0004d000 0x0004d000 0x001000>, /* ap 29 */
667 <0x00060000 0x00060000 0x001000>, /* ap 30 */
668 <0x00061000 0x00061000 0x001000>, /* ap 31 */
669 <0x00080000 0x00080000 0x010000>, /* ap 32 */
670 <0x00090000 0x00090000 0x001000>, /* ap 33 */
671 <0x00030000 0x00030000 0x001000>, /* ap 65 */
672 <0x00031000 0x00031000 0x001000>, /* ap 66 */
673 <0x0004a000 0x0004a000 0x001000>, /* ap 71 */
674 <0x0004b000 0x0004b000 0x001000>, /* ap 72 */
675 <0x000c8000 0x000c8000 0x001000>, /* ap 73 */
676 <0x000c9000 0x000c9000 0x001000>, /* ap 74 */
677 <0x000ca000 0x000ca000 0x001000>, /* ap 77 */
678 <0x000cb000 0x000cb000 0x001000>, /* ap 78 */
679 <0x00034000 0x00034000 0x001000>, /* ap 80 */
680 <0x00035000 0x00035000 0x001000>, /* ap 81 */
681 <0x00036000 0x00036000 0x001000>, /* ap 84 */
682 <0x00037000 0x00037000 0x001000>, /* ap 85 */
683 <0x46000000 0x46000000 0x400000>, /* l3 data port */
684 <0x46400000 0x46400000 0x400000>; /* l3 data port */
686 target-module@8000 { /* 0x48008000, ap 6 10.0 */
691 ranges = <0x0 0x8000 0x1000>;
694 target-module@22000 { /* 0x48022000, ap 8 0a.0 */
696 reg = <0x22050 0x4>,
697 <0x22054 0x4>,
698 <0x22058 0x4>;
708 clocks = <&l4ls_clkctrl AM4_L4LS_UART2_CLKCTRL 0>;
712 ranges = <0x0 0x22000 0x1000>;
714 uart1: serial@0 {
716 reg = <0x0 0x2000>;
722 target-module@24000 { /* 0x48024000, ap 10 1c.0 */
724 reg = <0x24050 0x4>,
725 <0x24054 0x4>,
726 <0x24058 0x4>;
736 clocks = <&l4ls_clkctrl AM4_L4LS_UART3_CLKCTRL 0>;
740 ranges = <0x0 0x24000 0x1000>;
742 uart2: serial@0 {
744 reg = <0x0 0x2000>;
750 target-module@2a000 { /* 0x4802a000, ap 12 22.0 */
752 reg = <0x2a000 0x8>,
753 <0x2a010 0x8>,
754 <0x2a090 0x8>;
766 clocks = <&l4ls_clkctrl AM4_L4LS_I2C2_CLKCTRL 0>;
770 ranges = <0x0 0x2a000 0x1000>;
772 i2c1: i2c@0 {
774 reg = <0x0 0x1000>;
777 #size-cells = <0>;
782 target-module@30000 { /* 0x48030000, ap 65 08.0 */
784 reg = <0x30000 0x4>,
785 <0x30110 0x4>,
786 <0x30114 0x4>;
796 clocks = <&l4ls_clkctrl AM4_L4LS_SPI0_CLKCTRL 0>;
800 ranges = <0x0 0x30000 0x1000>;
802 spi0: spi@0 {
804 reg = <0x0 0x400>;
807 #size-cells = <0>;
812 target-module@34000 { /* 0x48034000, ap 80 56.0 */
817 ranges = <0x0 0x34000 0x1000>;
820 target-module@36000 { /* 0x48036000, ap 84 3e.0 */
825 ranges = <0x0 0x36000 0x1000>;
828 target-module@38000 { /* 0x48038000, ap 14 04.0 */
830 reg = <0x38000 0x4>,
831 <0x38004 0x4>;
837 clocks = <&l3s_clkctrl AM4_L3S_MCASP0_CLKCTRL 0>;
841 ranges = <0x0 0x38000 0x2000>,
842 <0x46000000 0x46000000 0x400000>;
844 mcasp0: mcasp@0 {
846 reg = <0x0 0x2000>,
847 <0x46000000 0x400000>;
859 target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */
861 reg = <0x3c000 0x4>,
862 <0x3c004 0x4>;
868 clocks = <&l3s_clkctrl AM4_L3S_MCASP1_CLKCTRL 0>;
872 ranges = <0x0 0x3c000 0x2000>,
873 <0x46400000 0x46400000 0x400000>;
875 mcasp1: mcasp@0 {
877 reg = <0x0 0x2000>,
878 <0x46400000 0x400000>;
890 timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */
892 reg = <0x40000 0x4>,
893 <0x40010 0x4>,
894 <0x40014 0x4>;
902 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>;
906 ranges = <0x0 0x40000 0x1000>;
908 timer2: timer@0 {
910 reg = <0x0 0x400>;
917 target-module@42000 { /* 0x48042000, ap 20 24.0 */
919 reg = <0x42000 0x4>,
920 <0x42010 0x4>,
921 <0x42014 0x4>;
929 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER3_CLKCTRL 0>;
933 ranges = <0x0 0x42000 0x1000>;
935 timer3: timer@0 {
937 reg = <0x0 0x400>;
943 target-module@44000 { /* 0x48044000, ap 22 26.0 */
945 reg = <0x44000 0x4>,
946 <0x44010 0x4>,
947 <0x44014 0x4>;
955 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER4_CLKCTRL 0>;
959 ranges = <0x0 0x44000 0x1000>;
961 timer4: timer@0 {
963 reg = <0x0 0x400>;
970 target-module@46000 { /* 0x48046000, ap 24 28.0 */
972 reg = <0x46000 0x4>,
973 <0x46010 0x4>,
974 <0x46014 0x4>;
982 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER5_CLKCTRL 0>;
986 ranges = <0x0 0x46000 0x1000>;
988 timer5: timer@0 {
990 reg = <0x0 0x400>;
997 target-module@48000 { /* 0x48048000, ap 26 1a.0 */
999 reg = <0x48000 0x4>,
1000 <0x48010 0x4>,
1001 <0x48014 0x4>;
1009 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER6_CLKCTRL 0>;
1013 ranges = <0x0 0x48000 0x1000>;
1015 timer6: timer@0 {
1017 reg = <0x0 0x400>;
1024 target-module@4a000 { /* 0x4804a000, ap 71 48.0 */
1026 reg = <0x4a000 0x4>,
1027 <0x4a010 0x4>,
1028 <0x4a014 0x4>;
1036 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER7_CLKCTRL 0>;
1040 ranges = <0x0 0x4a000 0x1000>;
1042 timer7: timer@0 {
1044 reg = <0x0 0x400>;
1051 target-module@4c000 { /* 0x4804c000, ap 28 36.0 */
1053 reg = <0x4c000 0x4>,
1054 <0x4c010 0x4>,
1055 <0x4c114 0x4>;
1066 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 0>,
1071 ranges = <0x0 0x4c000 0x1000>;
1073 gpio1: gpio@0 {
1075 reg = <0x0 0x1000>;
1085 target-module@60000 { /* 0x48060000, ap 30 14.0 */
1087 reg = <0x602fc 0x4>,
1088 <0x60110 0x4>,
1089 <0x60114 0x4>;
1100 clocks = <&l4ls_clkctrl AM4_L4LS_MMC1_CLKCTRL 0>;
1104 ranges = <0x0 0x60000 0x1000>;
1106 mmc1: mmc@0 {
1108 reg = <0x0 0x1000>;
1110 dmas = <&edma 24 0>,
1111 <&edma 25 0>;
1118 target-module@80000 { /* 0x48080000, ap 32 18.0 */
1120 reg = <0x80000 0x4>,
1121 <0x80010 0x4>,
1122 <0x80014 0x4>;
1132 clocks = <&l4ls_clkctrl AM4_L4LS_ELM_CLKCTRL 0>;
1136 ranges = <0x0 0x80000 0x10000>;
1138 elm: elm@0 {
1140 reg = <0x0 0x2000>;
1148 target-module@c8000 { /* 0x480c8000, ap 73 06.0 */
1150 reg = <0xc8000 0x4>,
1151 <0xc8010 0x4>;
1158 clocks = <&l4ls_clkctrl AM4_L4LS_MAILBOX_CLKCTRL 0>;
1162 ranges = <0x0 0xc8000 0x1000>;
1164 mailbox: mailbox@0 {
1166 reg = <0x0 0x200>;
1173 ti,mbox-tx = <0 0 0>;
1174 ti,mbox-rx = <0 0 3>;
1179 target-module@ca000 { /* 0x480ca000, ap 77 38.0 */
1181 reg = <0xca000 0x4>,
1182 <0xca010 0x4>,
1183 <0xca014 0x4>;
1194 clocks = <&l4ls_clkctrl AM4_L4LS_SPINLOCK_CLKCTRL 0>;
1198 ranges = <0x0 0xca000 0x1000>;
1200 hwspinlock: spinlock@0 {
1202 reg = <0x0 0x1000>;
1208 segment@100000 { /* 0x48100000 */
1212 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */
1213 <0x0008d000 0x0018d000 0x001000>, /* ap 35 */
1214 <0x0008e000 0x0018e000 0x001000>, /* ap 36 */
1215 <0x0008f000 0x0018f000 0x001000>, /* ap 37 */
1216 <0x0009c000 0x0019c000 0x001000>, /* ap 38 */
1217 <0x0009d000 0x0019d000 0x001000>, /* ap 39 */
1218 <0x000a6000 0x001a6000 0x001000>, /* ap 40 */
1219 <0x000a7000 0x001a7000 0x001000>, /* ap 41 */
1220 <0x000a8000 0x001a8000 0x001000>, /* ap 42 */
1221 <0x000a9000 0x001a9000 0x001000>, /* ap 43 */
1222 <0x000aa000 0x001aa000 0x001000>, /* ap 44 */
1223 <0x000ab000 0x001ab000 0x001000>, /* ap 45 */
1224 <0x000ac000 0x001ac000 0x001000>, /* ap 46 */
1225 <0x000ad000 0x001ad000 0x001000>, /* ap 47 */
1226 <0x000ae000 0x001ae000 0x001000>, /* ap 48 */
1227 <0x000af000 0x001af000 0x001000>, /* ap 49 */
1228 <0x000cc000 0x001cc000 0x002000>, /* ap 50 */
1229 <0x000ce000 0x001ce000 0x002000>, /* ap 51 */
1230 <0x000d0000 0x001d0000 0x002000>, /* ap 52 */
1231 <0x000d2000 0x001d2000 0x002000>, /* ap 53 */
1232 <0x000d8000 0x001d8000 0x001000>, /* ap 54 */
1233 <0x000d9000 0x001d9000 0x001000>, /* ap 55 */
1234 <0x000a0000 0x001a0000 0x001000>, /* ap 67 */
1235 <0x000a1000 0x001a1000 0x001000>, /* ap 68 */
1236 <0x000a2000 0x001a2000 0x001000>, /* ap 69 */
1237 <0x000a3000 0x001a3000 0x001000>, /* ap 70 */
1238 <0x000a4000 0x001a4000 0x001000>, /* ap 92 */
1239 <0x000a5000 0x001a5000 0x001000>, /* ap 93 */
1240 <0x000c1000 0x001c1000 0x001000>, /* ap 94 */
1241 <0x000c2000 0x001c2000 0x001000>; /* ap 95 */
1243 target-module@8c000 { /* 0x4818c000, ap 34 0c.0 */
1248 ranges = <0x0 0x8c000 0x1000>;
1251 target-module@8e000 { /* 0x4818e000, ap 36 02.0 */
1256 ranges = <0x0 0x8e000 0x1000>;
1259 target-module@9c000 { /* 0x4819c000, ap 38 52.0 */
1261 reg = <0x9c000 0x8>,
1262 <0x9c010 0x8>,
1263 <0x9c090 0x8>;
1275 clocks = <&l4ls_clkctrl AM4_L4LS_I2C3_CLKCTRL 0>;
1279 ranges = <0x0 0x9c000 0x1000>;
1281 i2c2: i2c@0 {
1283 reg = <0x0 0x1000>;
1286 #size-cells = <0>;
1291 target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */
1293 reg = <0xa0000 0x4>,
1294 <0xa0110 0x4>,
1295 <0xa0114 0x4>;
1305 clocks = <&l4ls_clkctrl AM4_L4LS_SPI1_CLKCTRL 0>;
1309 ranges = <0x0 0xa0000 0x1000>;
1311 spi1: spi@0 {
1313 reg = <0x0 0x400>;
1316 #size-cells = <0>;
1321 target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */
1323 reg = <0xa2000 0x4>,
1324 <0xa2110 0x4>,
1325 <0xa2114 0x4>;
1335 clocks = <&l4ls_clkctrl AM4_L4LS_SPI2_CLKCTRL 0>;
1339 ranges = <0x0 0xa2000 0x1000>;
1341 spi2: spi@0 {
1343 reg = <0x0 0x400>;
1346 #size-cells = <0>;
1351 target-module@a4000 { /* 0x481a4000, ap 92 62.0 */
1353 reg = <0xa4000 0x4>,
1354 <0xa4110 0x4>,
1355 <0xa4114 0x4>;
1365 clocks = <&l4ls_clkctrl AM4_L4LS_SPI3_CLKCTRL 0>;
1369 ranges = <0x0 0xa4000 0x1000>;
1371 spi3: spi@0 {
1373 reg = <0x0 0x400>;
1376 #size-cells = <0>;
1381 target-module@a6000 { /* 0x481a6000, ap 40 16.0 */
1383 reg = <0xa6050 0x4>,
1384 <0xa6054 0x4>,
1385 <0xa6058 0x4>;
1395 clocks = <&l4ls_clkctrl AM4_L4LS_UART4_CLKCTRL 0>;
1399 ranges = <0x0 0xa6000 0x1000>;
1401 uart3: serial@0 {
1403 reg = <0x0 0x2000>;
1409 target-module@a8000 { /* 0x481a8000, ap 42 20.0 */
1411 reg = <0xa8050 0x4>,
1412 <0xa8054 0x4>,
1413 <0xa8058 0x4>;
1423 clocks = <&l4ls_clkctrl AM4_L4LS_UART5_CLKCTRL 0>;
1427 ranges = <0x0 0xa8000 0x1000>;
1429 uart4: serial@0 {
1431 reg = <0x0 0x2000>;
1437 target-module@aa000 { /* 0x481aa000, ap 44 12.0 */
1439 reg = <0xaa050 0x4>,
1440 <0xaa054 0x4>,
1441 <0xaa058 0x4>;
1451 clocks = <&l4ls_clkctrl AM4_L4LS_UART6_CLKCTRL 0>;
1455 ranges = <0x0 0xaa000 0x1000>;
1457 uart5: serial@0 {
1459 reg = <0x0 0x2000>;
1465 target-module@ac000 { /* 0x481ac000, ap 46 30.0 */
1467 reg = <0xac000 0x4>,
1468 <0xac010 0x4>,
1469 <0xac114 0x4>;
1480 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 0>,
1485 ranges = <0x0 0xac000 0x1000>;
1487 gpio2: gpio@0 {
1489 reg = <0x0 0x1000>;
1499 target-module@ae000 { /* 0x481ae000, ap 48 32.0 */
1501 reg = <0xae000 0x4>,
1502 <0xae010 0x4>,
1503 <0xae114 0x4>;
1514 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 0>,
1519 ranges = <0x0 0xae000 0x1000>;
1521 gpio3: gpio@0 {
1523 reg = <0x0 0x1000>;
1533 target-module@c1000 { /* 0x481c1000, ap 94 68.0 */
1535 reg = <0xc1000 0x4>,
1536 <0xc1010 0x4>,
1537 <0xc1014 0x4>;
1545 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER8_CLKCTRL 0>;
1549 ranges = <0x0 0xc1000 0x1000>;
1551 timer8: timer@0 {
1553 reg = <0x0 0x400>;
1559 target-module@cc000 { /* 0x481cc000, ap 50 46.0 */
1561 reg = <0xcc020 0x4>;
1564 clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>,
1569 ranges = <0x0 0xcc000 0x2000>;
1571 dcan0: can@0 {
1573 reg = <0x0 0x2000>;
1576 syscon-raminit = <&scm_conf 0x644 0>;
1582 target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */
1584 reg = <0xd0020 0x4>;
1587 clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>,
1592 ranges = <0x0 0xd0000 0x2000>;
1594 dcan1: can@0 {
1596 reg = <0x0 0x2000>;
1599 syscon-raminit = <&scm_conf 0x644 1>;
1605 target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */
1607 reg = <0xd82fc 0x4>,
1608 <0xd8110 0x4>,
1609 <0xd8114 0x4>;
1620 clocks = <&l4ls_clkctrl AM4_L4LS_MMC2_CLKCTRL 0>;
1624 ranges = <0x0 0xd8000 0x1000>;
1626 mmc2: mmc@0 {
1628 reg = <0x0 0x1000>;
1630 dmas = <&edma 2 0>,
1631 <&edma 3 0>;
1639 segment@200000 { /* 0x48200000 */
1643 ranges = <0x00000000 0x00200000 0x010000>;
1645 target-module@0 {
1648 clocks = <&mpu_clkctrl AM4_MPU_MPU_CLKCTRL 0>;
1653 ranges = <0 0 0x10000>;
1655 mpu@0 {
1663 segment@300000 { /* 0x48300000 */
1667 ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */
1668 <0x00001000 0x00301000 0x001000>, /* ap 57 */
1669 <0x00002000 0x00302000 0x001000>, /* ap 58 */
1670 <0x00003000 0x00303000 0x001000>, /* ap 59 */
1671 <0x00004000 0x00304000 0x001000>, /* ap 60 */
1672 <0x00005000 0x00305000 0x001000>, /* ap 61 */
1673 <0x00018000 0x00318000 0x004000>, /* ap 62 */
1674 <0x0001c000 0x0031c000 0x001000>, /* ap 63 */
1675 <0x00010000 0x00310000 0x002000>, /* ap 64 */
1676 <0x00028000 0x00328000 0x001000>, /* ap 75 */
1677 <0x00029000 0x00329000 0x001000>, /* ap 76 */
1678 <0x00012000 0x00312000 0x001000>, /* ap 79 */
1679 <0x00020000 0x00320000 0x001000>, /* ap 82 */
1680 <0x00021000 0x00321000 0x001000>, /* ap 83 */
1681 <0x00026000 0x00326000 0x001000>, /* ap 86 */
1682 <0x00027000 0x00327000 0x001000>, /* ap 87 */
1683 <0x0002a000 0x0032a000 0x000400>, /* ap 88 */
1684 <0x0002c000 0x0032c000 0x001000>, /* ap 89 */
1685 <0x00013000 0x00313000 0x001000>, /* ap 90 */
1686 <0x00014000 0x00314000 0x001000>, /* ap 91 */
1687 <0x00006000 0x00306000 0x001000>, /* ap 96 */
1688 <0x00007000 0x00307000 0x001000>, /* ap 97 */
1689 <0x00008000 0x00308000 0x001000>, /* ap 98 */
1690 <0x00009000 0x00309000 0x001000>, /* ap 99 */
1691 <0x0000a000 0x0030a000 0x001000>, /* ap 100 */
1692 <0x0000b000 0x0030b000 0x001000>, /* ap 101 */
1693 <0x0003d000 0x0033d000 0x001000>, /* ap 102 */
1694 <0x0003e000 0x0033e000 0x001000>, /* ap 103 */
1695 <0x0003f000 0x0033f000 0x001000>, /* ap 104 */
1696 <0x00040000 0x00340000 0x001000>, /* ap 105 */
1697 <0x00041000 0x00341000 0x001000>, /* ap 106 */
1698 <0x00042000 0x00342000 0x001000>, /* ap 107 */
1699 <0x00045000 0x00345000 0x001000>, /* ap 108 */
1700 <0x00046000 0x00346000 0x001000>, /* ap 109 */
1701 <0x00047000 0x00347000 0x001000>, /* ap 110 */
1702 <0x00048000 0x00348000 0x001000>, /* ap 111 */
1703 <0x000f2000 0x003f2000 0x002000>, /* ap 112 */
1704 <0x000f4000 0x003f4000 0x001000>, /* ap 113 */
1705 <0x0004c000 0x0034c000 0x002000>, /* ap 114 */
1706 <0x0004e000 0x0034e000 0x001000>, /* ap 115 */
1707 <0x00022000 0x00322000 0x001000>, /* ap 116 */
1708 <0x00023000 0x00323000 0x001000>, /* ap 117 */
1709 <0x000f0000 0x003f0000 0x001000>, /* ap 118 */
1710 <0x0002a400 0x0032a400 0x000400>, /* ap 119 */
1711 <0x0002a800 0x0032a800 0x000400>, /* ap 120 */
1712 <0x0002ac00 0x0032ac00 0x000400>, /* ap 121 */
1713 <0x0002b000 0x0032b000 0x001000>, /* ap 122 */
1714 <0x00080000 0x00380000 0x020000>, /* ap 123 */
1715 <0x000a0000 0x003a0000 0x001000>, /* ap 124 */
1716 <0x000a8000 0x003a8000 0x008000>, /* ap 125 */
1717 <0x000b0000 0x003b0000 0x001000>, /* ap 126 */
1718 <0x000c0000 0x003c0000 0x020000>, /* ap 127 */
1719 <0x000e0000 0x003e0000 0x001000>, /* ap 128 */
1720 <0x000e8000 0x003e8000 0x008000>; /* ap 129 */
1722 target-module@0 { /* 0x48300000, ap 56 40.0 */
1724 reg = <0x0 0x4>,
1725 <0x4 0x4>;
1736 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS0_CLKCTRL 0>;
1740 ranges = <0x0 0x0 0x1000>;
1742 epwmss0: epwmss@0 {
1744 reg = <0x0 0x10>;
1747 ranges = <0 0 0x1000>;
1754 reg = <0x100 0x80>;
1764 reg = <0x200 0x80>;
1772 target-module@2000 { /* 0x48302000, ap 58 4a.0 */
1774 reg = <0x2000 0x4>,
1775 <0x2004 0x4>;
1786 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS1_CLKCTRL 0>;
1790 ranges = <0x0 0x2000 0x1000>;
1792 epwmss1: epwmss@0 {
1794 reg = <0x0 0x10>;
1797 ranges = <0 0 0x1000>;
1804 reg = <0x100 0x80>;
1814 reg = <0x200 0x80>;
1822 target-module@4000 { /* 0x48304000, ap 60 44.0 */
1824 reg = <0x4000 0x4>,
1825 <0x4004 0x4>;
1836 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS2_CLKCTRL 0>;
1840 ranges = <0x0 0x4000 0x1000>;
1842 epwmss2: epwmss@0 {
1844 reg = <0x0 0x10>;
1847 ranges = <0 0 0x1000>;
1854 reg = <0x100 0x80>;
1864 reg = <0x200 0x80>;
1872 target-module@6000 { /* 0x48306000, ap 96 58.0 */
1874 reg = <0x6000 0x4>,
1875 <0x6004 0x4>;
1886 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS3_CLKCTRL 0>;
1890 ranges = <0x0 0x6000 0x1000>;
1892 epwmss3: epwmss@0 {
1894 reg = <0x0 0x10>;
1897 ranges = <0 0 0x1000>;
1904 reg = <0x200 0x80>;
1912 target-module@8000 { /* 0x48308000, ap 98 54.0 */
1914 reg = <0x8000 0x4>,
1915 <0x8004 0x4>;
1926 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS4_CLKCTRL 0>;
1930 ranges = <0x0 0x8000 0x1000>;
1932 epwmss4: epwmss@0 {
1934 reg = <0x0 0x10>;
1937 ranges = <0 0 0x1000>;
1944 reg = <0x200 0x80>;
1952 target-module@a000 { /* 0x4830a000, ap 100 60.0 */
1954 reg = <0xa000 0x4>,
1955 <0xa004 0x4>;
1966 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS5_CLKCTRL 0>;
1970 ranges = <0x0 0xa000 0x1000>;
1972 epwmss5: epwmss@0 {
1974 reg = <0x0 0x10>;
1977 ranges = <0 0 0x1000>;
1984 reg = <0x200 0x80>;
1992 target-module@10000 { /* 0x48310000, ap 64 4e.1 */
1994 reg = <0x11fe0 0x4>,
1995 <0x11fe4 0x4>;
2001 clocks = <&l4ls_clkctrl AM4_L4LS_RNG_CLKCTRL 0>;
2005 ranges = <0x0 0x10000 0x2000>;
2007 rng: rng@0 {
2009 reg = <0x0 0x2000>;
2014 target-module@13000 { /* 0x48313000, ap 90 50.0 */
2019 ranges = <0x0 0x13000 0x1000>;
2022 target-module@18000 { /* 0x48318000, ap 62 4c.0 */
2027 ranges = <0x0 0x18000 0x4000>;
2030 target-module@20000 { /* 0x48320000, ap 82 34.0 */
2032 reg = <0x20000 0x4>,
2033 <0x20010 0x4>,
2034 <0x20114 0x4>;
2045 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 0>,
2050 ranges = <0x0 0x20000 0x1000>;
2052 gpio4: gpio@0 {
2054 reg = <0x0 0x1000>;
2064 gpio5_target: target-module@22000 { /* 0x48322000, ap 116 64.0 */
2066 reg = <0x22000 0x4>,
2067 <0x22010 0x4>,
2068 <0x22114 0x4>;
2079 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 0>,
2084 ranges = <0x0 0x22000 0x1000>;
2086 gpio5: gpio@0 {
2088 reg = <0x0 0x1000>;
2098 target-module@26000 { /* 0x48326000, ap 86 66.0 */
2100 reg = <0x26000 0x4>,
2101 <0x26104 0x4>;
2110 clocks = <&l3s_clkctrl AM4_L3S_VPFE0_CLKCTRL 0>;
2114 ranges = <0x0 0x26000 0x1000>;
2116 vpfe0: vpfe@0 {
2118 reg = <0x0 0x2000>;
2124 target-module@28000 { /* 0x48328000, ap 75 0e.0 */
2126 reg = <0x28000 0x4>,
2127 <0x28104 0x4>;
2136 clocks = <&l3s_clkctrl AM4_L3S_VPFE1_CLKCTRL 0>;
2140 ranges = <0x0 0x28000 0x1000>;
2142 vpfe1: vpfe@0 {
2144 reg = <0x0 0x2000>;
2150 target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */
2152 reg = <0x2a000 0x4>,
2153 <0x2a010 0x4>,
2154 <0x2a014 0x4>;
2160 clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
2164 ranges = <0x00000000 0x0002a000 0x00000400>,
2165 <0x00000400 0x0002a400 0x00000400>,
2166 <0x00000800 0x0002a800 0x00000400>,
2167 <0x00000c00 0x0002ac00 0x00000400>,
2168 <0x00001000 0x0002b000 0x00001000>;
2170 dss: dss@0 {
2172 reg = <0 0x200>;
2178 ranges = <0x00000000 0x00000000 0x00000400>,
2179 <0x00000400 0x00000400 0x00000400>,
2180 <0x00000800 0x00000800 0x00000400>,
2181 <0x00000c00 0x00000c00 0x00000400>,
2182 <0x00001000 0x00001000 0x00001000>;
2186 reg = <0x400 0x4>,
2187 <0x410 0x4>,
2188 <0x414 0x4>;
2201 clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
2205 ranges = <0 0x400 0x400>;
2207 dispc: dispc@0 {
2209 reg = <0 0x400>;
2220 reg = <0x800 0x4>,
2221 <0x810 0x4>,
2222 <0x814 0x4>;
2230 clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
2234 ranges = <0 0x800 0x400>;
2236 rfbi: rfbi@0 {
2238 reg = <0 0x100>;
2239 clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
2247 target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */
2249 reg = <0x3d000 0x4>,
2250 <0x3d010 0x4>,
2251 <0x3d014 0x4>;
2259 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER9_CLKCTRL 0>;
2263 ranges = <0x0 0x3d000 0x1000>;
2265 timer9: timer@0 {
2267 reg = <0x0 0x400>;
2273 target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */
2275 reg = <0x3f000 0x4>,
2276 <0x3f010 0x4>,
2277 <0x3f014 0x4>;
2285 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER10_CLKCTRL 0>;
2289 ranges = <0x0 0x3f000 0x1000>;
2291 timer10: timer@0 {
2293 reg = <0x0 0x400>;
2299 target-module@41000 { /* 0x48341000, ap 106 76.0 */
2301 reg = <0x41000 0x4>,
2302 <0x41010 0x4>,
2303 <0x41014 0x4>;
2311 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER11_CLKCTRL 0>;
2315 ranges = <0x0 0x41000 0x1000>;
2317 timer11: timer@0 {
2319 reg = <0x0 0x400>;
2325 target-module@45000 { /* 0x48345000, ap 108 6a.0 */
2327 reg = <0x45000 0x4>,
2328 <0x45110 0x4>,
2329 <0x45114 0x4>;
2339 clocks = <&l4ls_clkctrl AM4_L4LS_SPI4_CLKCTRL 0>;
2343 ranges = <0x0 0x45000 0x1000>;
2345 spi4: spi@0 {
2347 reg = <0x0 0x400>;
2350 #size-cells = <0>;
2355 target-module@47000 { /* 0x48347000, ap 110 70.0 */
2357 reg = <0x47000 0x4>,
2358 <0x47014 0x4>,
2359 <0x47018 0x4>;
2364 clocks = <&l4ls_clkctrl AM4_L4LS_HDQ1W_CLKCTRL 0>;
2368 ranges = <0x0 0x47000 0x1000>;
2370 hdq: hdq@0 {
2372 reg = <0x0 0x1000>;
2380 target-module@4c000 { /* 0x4834c000, ap 114 72.0 */
2382 reg = <0x4c000 0x4>,
2383 <0x4c010 0x4>;
2388 clocks = <&l3s_clkctrl AM4_L3S_ADC1_CLKCTRL 0>;
2392 ranges = <0x0 0x4c000 0x2000>;
2394 magadc: magadc@0 {
2396 reg = <0x0 0x2000>;
2400 dmas = <&edma 54 0>, <&edma 55 0>;
2415 target-module@80000 { /* 0x48380000, ap 123 42.0 */
2417 reg = <0x80000 0x4>,
2418 <0x80010 0x4>;
2430 clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 0>;
2434 ranges = <0x0 0x80000 0x20000>;
2436 dwc3_1: omap_dwc3@0 {
2438 reg = <0x0 0x10000>;
2443 ranges = <0 0 0x20000>;
2447 reg = <0x10000 0x10000>;
2465 target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */
2467 reg = <0xa8000 0x4>;
2470 clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP0_CLKCTRL 0>;
2474 ranges = <0x0 0xa8000 0x8000>;
2476 ocp2scp0: ocp2scp@0 {
2480 ranges = <0 0 0x8000>;
2484 reg = <0x0 0x8000>;
2485 syscon-phy-power = <&scm_conf 0x620>;
2489 #phy-cells = <0>;
2495 target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */
2497 reg = <0xc0000 0x4>,
2498 <0xc0010 0x4>;
2510 clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 0>;
2514 ranges = <0x0 0xc0000 0x20000>;
2516 dwc3_2: omap_dwc3@0 {
2518 reg = <0x0 0x10000>;
2523 ranges = <0 0 0x20000>;
2527 reg = <0x10000 0x10000>;
2545 target-module@e8000 { /* 0x483e8000, ap 129 78.0 */
2547 reg = <0xe8000 0x4>;
2550 clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP1_CLKCTRL 0>;
2554 ranges = <0x0 0xe8000 0x8000>;
2556 ocp2scp1: ocp2scp@0 {
2560 ranges = <0 0 0x8000>;
2564 reg = <0x0 0x8000>;
2565 syscon-phy-power = <&scm_conf 0x628>;
2569 #phy-cells = <0>;
2575 target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */
2580 ranges = <0x0 0xf2000 0x2000>;