Lines Matching +full:dsp +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/reset/ti-syscon.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
18 interrupt-parent = <&gic>;
21 compatible = "arm,cortex-a15";
27 compatible = "arm,cortex-a15";
42 /include/ "keystone-k2l-clocks.dtsi"
45 compatible = "ti,da830-uart", "ns16550a";
46 current-speed = <115200>;
47 reg-shift = <2>;
48 reg-io-width = <4>;
55 compatible = "ti,da830-uart", "ns16550a";
56 current-speed = <115200>;
57 reg-shift = <2>;
58 reg-io-width = <4>;
65 compatible = "ti,keystone-gpio";
67 gpio-controller;
68 #gpio-cells = <2>;
103 clock-names = "gpio";
105 ti,davinci-gpio-unbanked = <32>;
109 compatible = "pinctrl-single";
111 #address-cells = <1>;
112 #size-cells = <0>;
113 #pinctrl-cells = <2>;
114 pinctrl-single,bit-per-mux;
115 pinctrl-single,register-width = <32>;
116 pinctrl-single,function-mask = <0x1>;
119 uart3_emifa_pins: uart3-emifa-pins {
120 pinctrl-single,bits = <
126 uart2_emifa_pins: uart2-emifa-pins {
127 pinctrl-single,bits = <
133 uart01_spi2_pins: uart01-spi2-pins {
134 pinctrl-single,bits = <
140 dfesync_rp1_pins: dfesync-rp1-pins {
141 pinctrl-single,bits = <
147 avsif_pins: avsif-pins {
148 pinctrl-single,bits = <
154 gpio_emu_pins: gpio-emu-pins {
155 pinctrl-single,bits = <
157 * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33
158 * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32
159 * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31
160 * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30
161 * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29
162 * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28
163 * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27
164 * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26
165 * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25
166 * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24
167 * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23
168 * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22
169 * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21
170 * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20
171 * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19
177 gpio_timio_pins: gpio-timio-pins {
178 pinctrl-single,bits = <
180 * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7
181 * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6
182 * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5
183 * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4
184 * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3
185 * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2
186 * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7
187 * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6
188 * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5
189 * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4
190 * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3
191 * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2
197 gpio_spi2cs_pins: gpio-spi2cs-pins {
198 pinctrl-single,bits = <
200 * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4
201 * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3
202 * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2
203 * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1
209 gpio_dfeio_pins: gpio-dfeio-pins {
210 pinctrl-single,bits = <
212 * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63
213 * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62
214 * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61
215 * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60
216 * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59
217 * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58
218 * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57
219 * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56
220 * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55
221 * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54
222 * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53
223 * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52
224 * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51
225 * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50
226 * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49
227 * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48
233 gpio_emifa_pins: gpio-emifa-pins {
234 pinctrl-single,bits = <
236 * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47
237 * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46
238 * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45
239 * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44
240 * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43
241 * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42
242 * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41
243 * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40
244 * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39
245 * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38
246 * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37
247 * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36
248 * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35
249 * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34
250 * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33
251 * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32
259 compatible = "mmio-sram";
262 #address-cells = <1>;
263 #size-cells = <1>;
265 bm-sram@1f8000 {
270 psc: power-sleep-controller@2350000 {
271 pscrst: reset-controller {
272 compatible = "ti,k2l-pscrst", "ti,syscon-reset";
273 #reset-cells = <1>;
275 ti,reset-bits = <
285 compatible = "mmio-sram";
287 #address-cells = <1>;
288 #size-cells = <1>;
292 devctrl: device-state-control@2620000 {
294 compatible = "ti,keystone-dsp-gpio";
296 gpio-controller;
297 #gpio-cells = <2>;
298 gpio,syscon-dev = <&devctrl 0x240>;
302 compatible = "ti,keystone-dsp-gpio";
304 gpio-controller;
305 #gpio-cells = <2>;
306 gpio,syscon-dev = <&devctrl 0x244>;
310 compatible = "ti,keystone-dsp-gpio";
312 gpio-controller;
313 #gpio-cells = <2>;
314 gpio,syscon-dev = <&devctrl 0x248>;
318 compatible = "ti,keystone-dsp-gpio";
320 gpio-controller;
321 #gpio-cells = <2>;
322 gpio,syscon-dev = <&devctrl 0x24c>;
326 dsp0: dsp@10800000 {
327 compatible = "ti,k2l-dsp";
331 reg-names = "l2sram", "l1pram", "l1dram";
333 ti,syscon-dev = <&devctrl 0x844>;
335 interrupt-parent = <&kirq0>;
337 interrupt-names = "vring", "exception";
338 kick-gpios = <&dspgpio0 27 0>;
342 dsp1: dsp@11800000 {
343 compatible = "ti,k2l-dsp";
347 reg-names = "l2sram", "l1pram", "l1dram";
349 ti,syscon-dev = <&devctrl 0x848>;
351 interrupt-parent = <&kirq0>;
353 interrupt-names = "vring", "exception";
354 kick-gpios = <&dspgpio1 27 0>;
358 dsp2: dsp@12800000 {
359 compatible = "ti,k2l-dsp";
363 reg-names = "l2sram", "l1pram", "l1dram";
365 ti,syscon-dev = <&devctrl 0x84c>;
367 interrupt-parent = <&kirq0>;
369 interrupt-names = "vring", "exception";
370 kick-gpios = <&dspgpio2 27 0>;
374 dsp3: dsp@13800000 {
375 compatible = "ti,k2l-dsp";
379 reg-names = "l2sram", "l1pram", "l1dram";
381 ti,syscon-dev = <&devctrl 0x850>;
383 interrupt-parent = <&kirq0>;
385 interrupt-names = "vring", "exception";
386 kick-gpios = <&dspgpio3 27 0>;
392 #address-cells = <1>;
393 #size-cells = <0>;
397 clock-names = "fck";
400 /include/ "keystone-k2l-netcp.dtsi"
404 ti,davinci-spi-num-cs = <5>;
408 ti,davinci-spi-num-cs = <3>;
412 ti,davinci-spi-num-cs = <5>;