Lines Matching +full:0 +full:x23100000
33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
46 reg = <0x0 0x02561000 0x0 0x1000>,
47 <0x0 0x02562000 0x0 0x2000>,
48 <0x0 0x02564000 0x0 0x2000>,
49 <0x0 0x02566000 0x0 0x2000>;
74 #size-cells = <0>;
77 usb0_phy: usb-phy@0 {
79 reg = <0>;
90 soc0: soc@0 {
95 ranges = <0x0 0x0 0x0 0xc0000000>;
96 dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
100 reg = <0x0c000000 0x100000>;
101 ranges = <0x0 0x0c000000 0x100000>;
106 reg = <0x000f7000 0x8000>;
112 reg = <0x02621000 0x410>;
114 pinctrl-single,function-mask = <0x001b0007>;
119 reg = <0x02620000 0x1000>;
122 ranges = <0x0 0x02620000 0x1000>;
126 reg = <0x2a0 0x10>;
130 ti,syscon-dev = <&devctrl 0x2a0>;
135 reg = <0x240 0x4>;
138 gpio,syscon-dev = <&devctrl 0x240>;
147 reg = <0x02530c00 0x100>;
149 clocks = <&k2g_clks 0x2c 0>;
150 power-domains = <&k2g_pds 0x2c>;
159 reg = <0x02531000 0x100>;
161 clocks = <&k2g_clks 0x2d 0>;
162 power-domains = <&k2g_pds 0x2d>;
171 reg = <0x02531400 0x100>;
173 clocks = <&k2g_clks 0x2e 0>;
174 power-domains = <&k2g_pds 0x2e>;
180 reg = <0x0260b200 0x200>;
183 power-domains = <&k2g_pds 0x0008>;
184 clocks = <&k2g_clks 0x0008 1>;
189 reg = <0x0260b400 0x200>;
192 power-domains = <&k2g_pds 0x0009>;
193 clocks = <&k2g_clks 0x0009 1>;
198 reg = <0x02530000 0x400>;
199 clocks = <&k2g_clks 0x003a 0>;
200 power-domains = <&k2g_pds 0x003a>;
203 #size-cells = <0>;
209 reg = <0x02530400 0x400>;
210 clocks = <&k2g_clks 0x003b 0>;
211 power-domains = <&k2g_pds 0x003b>;
214 #size-cells = <0>;
220 reg = <0x02530800 0x400>;
221 clocks = <&k2g_clks 0x003c 0>;
222 power-domains = <&k2g_pds 0x003c>;
225 #size-cells = <0>;
231 reg = <0x10800000 0x00100000>,
232 <0x10e00000 0x00008000>,
233 <0x10f00000 0x00008000>;
235 power-domains = <&k2g_pds 0x0046>;
236 ti,syscon-dev = <&devctrl 0x844>;
237 resets = <&k2g_reset 0x0046 0x1>;
239 interrupts = <0 8>;
241 kick-gpios = <&dspgpio0 27 0>;
250 reg = <0x02a00000 0x400000>, <0x028c3400 0x400>;
261 <&msgmgr 0 0>;
263 reg = <0x02921c00 0x400>;
283 reg = <0x02603000 0x100>;
299 ti,davinci-gpio-unbanked = <0>;
300 clocks = <&k2g_clks 0x001b 0x0>;
306 reg = <0x0260a000 0x100>;
317 ti,davinci-gpio-unbanked = <0>;
318 clocks = <&k2g_clks 0x001c 0x0>;
324 reg = <0x02540000 0x400>,
325 <0x02550000 0x1000>,
326 <0x02557000 0x1000>,
327 <0x0255a800 0x100>,
328 <0x0255ac00 0x100>;
330 clocks = <&k2g_clks 0x2 0>,
331 <&k2g_clks 0x2 1>;
335 power-domains = <&k2g_pds 0x2>;
346 reg = <0x02700000 0x8000>;
356 ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
360 power-domains = <&k2g_pds 0x3f>;
365 reg = <0x02760000 0x400>;
366 power-domains = <&k2g_pds 0x3f>;
371 reg = <0x02768000 0x400>;
372 power-domains = <&k2g_pds 0x3f>;
377 reg = <0x02728000 0x8000>;
387 ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
395 power-domains = <&k2g_pds 0x4f>;
400 reg = <0x027b0000 0x400>;
401 power-domains = <&k2g_pds 0x4f>;
406 reg = <0x027b8000 0x400>;
407 power-domains = <&k2g_pds 0x4f>;
412 reg = <0x23000000 0x400>;
417 power-domains = <&k2g_pds 0xb>;
418 clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
425 reg = <0x23100000 0x400>;
431 power-domains = <&k2g_pds 0xc>;
432 clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>;
439 #size-cells = <0>;
440 reg = <0x02940000 0x1000>,
441 <0x24000000 0x4000000>;
445 cdns,trigger-address = <0x24000000>;
446 clocks = <&k2g_clks 0x43 0x0>;
447 power-domains = <&k2g_pds 0x43>;
453 reg = <0x02340000 0x2000>,
454 <0x21804000 0x1000>;
461 power-domains = <&k2g_pds 0x4>;
462 clocks = <&k2g_clks 0x4 0>;
469 reg = <0x02342000 0x2000>,
470 <0x21804400 0x1000>;
477 power-domains = <&k2g_pds 0x5>;
478 clocks = <&k2g_clks 0x5 0>;
485 reg = <0x02344000 0x2000>,
486 <0x21804800 0x1000>;
493 power-domains = <&k2g_pds 0x6>;
494 clocks = <&k2g_clks 0x6 0>;
503 reg = <0x2680000 0x10000>;
509 power-domains = <&k2g_pds 0x0016>;
513 reg = <0x2690000 0x10000>;
526 reg = <0x2580000 0x10000>;
532 power-domains = <&k2g_pds 0x0017>;
536 reg = <0x2590000 0x10000>;
548 reg = <0x021d1800 0x60>;
549 power-domains = <&k2g_pds 0x38>;
550 clocks = <&k2g_clks 0x38 0>;
558 reg = <0x021d1c00 0x60>;
559 power-domains = <&k2g_pds 0x39>;
560 clocks = <&k2g_clks 0x39 0x0>;
567 reg = <0x21805400 0x200>;
569 ti,davinci-spi-intr-line = <0>;
572 #size-cells = <0>;
573 power-domains = <&k2g_pds 0x0010>;
574 clocks = <&k2g_clks 0x0010 0>;
579 reg = <0x21805800 0x200>;
581 ti,davinci-spi-intr-line = <0>;
584 #size-cells = <0>;
585 power-domains = <&k2g_pds 0x0011>;
586 clocks = <&k2g_clks 0x0011 0>;
591 reg = <0x21805c00 0x200>;
593 ti,davinci-spi-intr-line = <0>;
596 #size-cells = <0>;
597 power-domains = <&k2g_pds 0x0012>;
598 clocks = <&k2g_clks 0x0012 0>;
603 reg = <0x21806000 0x200>;
605 ti,davinci-spi-intr-line = <0>;
608 #size-cells = <0>;
609 power-domains = <&k2g_pds 0x0013>;
610 clocks = <&k2g_clks 0x0013 0>;
615 reg = <0x02250000 0x80>;
616 power-domains = <&k2g_pds 0x22>;
617 clocks = <&k2g_clks 0x22 0>;
622 reg = <0x21010000 0x200>;
628 reg = <0x04200f00 0x100>;
630 #size-cells = <0>;
631 clocks = <&k2g_clks 0x0018 3>;
633 power-domains = <&k2g_pds 0x0018>;