Lines Matching +full:gic +full:- +full:timer
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,berlin-smp";
34 next-level-cache = <&l2>;
38 clock-latency = <100000>;
39 operating-points = <
51 next-level-cache = <&l2>;
55 clock-latency = <100000>;
56 operating-points = <
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <25000000>;
73 compatible = "simple-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 interrupt-parent = <&gic>;
81 compatible = "mrvl,pxav3-mmc";
84 clock-names = "io", "core";
90 compatible = "mrvl,pxav3-mmc";
93 clock-names = "io", "core";
99 compatible = "mrvl,pxav3-mmc";
103 clock-names = "io", "core";
104 pinctrl-0 = <&emmc_pmux>;
105 pinctrl-names = "default";
109 l2: cache-controller@ac0000 {
110 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
112 cache-unified;
113 cache-level = <2>;
116 scu: snoop-control-unit@ad0000 {
117 compatible = "arm,cortex-a9-scu";
121 gic: interrupt-controller@ad1000 { label
122 compatible = "arm,cortex-a9-gic";
124 interrupt-controller;
125 #interrupt-cells = <3>;
128 local-timer@ad0600 {
129 compatible = "arm,cortex-a9-twd-timer";
136 compatible = "marvell,pxa168-eth";
141 local-mac-address = [00 00 00 00 00 00];
142 #address-cells = <1>;
143 #size-cells = <0>;
144 phy-connection-type = "mii";
145 phy-handle = <ðphy1>;
148 ethphy1: ethernet-phy@0 {
153 cpu-ctrl@dd0000 {
154 compatible = "marvell,berlin-cpu-ctrl";
159 compatible = "marvell,pxa168-eth";
164 local-mac-address = [00 00 00 00 00 00];
165 #address-cells = <1>;
166 #size-cells = <0>;
167 phy-connection-type = "mii";
168 phy-handle = <ðphy0>;
171 ethphy0: ethernet-phy@0 {
177 compatible = "simple-bus";
178 #address-cells = <1>;
179 #size-cells = <1>;
182 interrupt-parent = <&aic>;
185 compatible = "snps,dw-apb-gpio";
187 #address-cells = <1>;
188 #size-cells = <0>;
190 porta: gpio-port@0 {
191 compatible = "snps,dw-apb-gpio-port";
192 gpio-controller;
193 #gpio-cells = <2>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
203 compatible = "snps,dw-apb-gpio";
205 #address-cells = <1>;
206 #size-cells = <0>;
208 portb: gpio-port@1 {
209 compatible = "snps,dw-apb-gpio-port";
210 gpio-controller;
211 #gpio-cells = <2>;
214 interrupt-controller;
215 #interrupt-cells = <2>;
221 compatible = "snps,dw-apb-gpio";
223 #address-cells = <1>;
224 #size-cells = <0>;
226 portc: gpio-port@2 {
227 compatible = "snps,dw-apb-gpio-port";
228 gpio-controller;
229 #gpio-cells = <2>;
232 interrupt-controller;
233 #interrupt-cells = <2>;
239 compatible = "snps,dw-apb-gpio";
241 #address-cells = <1>;
242 #size-cells = <0>;
244 portd: gpio-port@3 {
245 compatible = "snps,dw-apb-gpio-port";
246 gpio-controller;
247 #gpio-cells = <2>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
256 timer0: timer@2c00 {
257 compatible = "snps,dw-apb-timer";
261 clock-names = "timer";
265 timer1: timer@2c14 {
266 compatible = "snps,dw-apb-timer";
270 clock-names = "timer";
274 timer2: timer@2c28 {
275 compatible = "snps,dw-apb-timer";
279 clock-names = "timer";
283 timer3: timer@2c3c {
284 compatible = "snps,dw-apb-timer";
288 clock-names = "timer";
292 timer4: timer@2c50 {
293 compatible = "snps,dw-apb-timer";
297 clock-names = "timer";
301 timer5: timer@2c64 {
302 compatible = "snps,dw-apb-timer";
306 clock-names = "timer";
310 timer6: timer@2c78 {
311 compatible = "snps,dw-apb-timer";
315 clock-names = "timer";
319 timer7: timer@2c8c {
320 compatible = "snps,dw-apb-timer";
324 clock-names = "timer";
328 aic: interrupt-controller@3000 {
329 compatible = "snps,dw-apb-ictl";
331 interrupt-controller;
332 #interrupt-cells = <1>;
333 interrupt-parent = <&gic>;
339 compatible = "marvell,berlin2-ahci", "generic-ahci";
343 #address-cells = <1>;
344 #size-cells = <0>;
346 sata0: sata-port@0 {
352 sata1: sata-port@1 {
360 compatible = "marvell,berlin2-sata-phy";
363 #address-cells = <1>;
364 #size-cells = <0>;
365 #phy-cells = <1>;
368 sata-phy@0 {
372 sata-phy@1 {
377 chip: chip-control@ea0000 {
378 compatible = "simple-mfd", "syscon";
382 compatible = "marvell,berlin2-clk";
383 #clock-cells = <1>;
385 clock-names = "refclk";
388 soc_pinctrl: pin-controller {
389 compatible = "marvell,berlin2-soc-pinctrl";
391 emmc_pmux: emmc-pmux {
398 compatible = "marvell,berlin2-reset";
399 #reset-cells = <2>;
404 compatible = "marvell,berlin-pwm";
407 #pwm-cells = <3>;
411 compatible = "simple-bus";
412 #address-cells = <1>;
413 #size-cells = <1>;
416 interrupt-parent = <&sic>;
419 compatible = "snps,dw-wdt";
426 compatible = "snps,dw-wdt";
433 compatible = "snps,dw-wdt";
440 compatible = "snps,dw-apb-gpio";
442 #address-cells = <1>;
443 #size-cells = <0>;
445 portf: gpio-port@5 {
446 compatible = "snps,dw-apb-gpio-port";
447 gpio-controller;
448 #gpio-cells = <2>;
455 compatible = "snps,dw-apb-gpio";
457 #address-cells = <1>;
458 #size-cells = <0>;
460 porte: gpio-port@4 {
461 compatible = "snps,dw-apb-gpio-port";
462 gpio-controller;
463 #gpio-cells = <2>;
466 interrupt-controller;
467 #interrupt-cells = <2>;
473 compatible = "snps,dw-apb-uart";
475 reg-shift = <2>;
476 reg-io-width = <1>;
479 pinctrl-0 = <&uart0_pmux>;
480 pinctrl-names = "default";
485 compatible = "snps,dw-apb-uart";
487 reg-shift = <2>;
488 reg-io-width = <1>;
491 pinctrl-0 = <&uart1_pmux>;
492 pinctrl-names = "default";
497 compatible = "snps,dw-apb-uart";
499 reg-shift = <2>;
500 reg-io-width = <1>;
503 pinctrl-0 = <&uart2_pmux>;
504 pinctrl-names = "default";
508 sysctrl: system-controller@d000 {
509 compatible = "simple-mfd", "syscon";
512 sys_pinctrl: pin-controller {
513 compatible = "marvell,berlin2-system-pinctrl";
514 uart0_pmux: uart0-pmux {
519 uart1_pmux: uart1-pmux {
523 uart2_pmux: uart2-pmux {
530 sic: interrupt-controller@e000 {
531 compatible = "snps,dw-apb-ictl";
533 interrupt-controller;
534 #interrupt-cells = <1>;
535 interrupt-parent = <&gic>;