Lines Matching +full:stm32 +full:- +full:rcc
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
53 clk_hse: clk-hse {
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
56 clock-frequency = <0>;
59 clk-lse {
60 #clock-cells = <0>;
61 compatible = "fixed-clock";
62 clock-frequency = <32768>;
65 clk-lsi {
66 #clock-cells = <0>;
67 compatible = "fixed-clock";
68 clock-frequency = <32000>;
71 clk_i2s_ckin: clk-i2s-ckin {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <48000000>;
80 #address-cells = <1>;
81 #size-cells = <0>;
82 compatible = "st,stm32-timers";
84 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
85 clock-names = "int";
89 compatible = "st,stm32-pwm";
90 #pwm-cells = <3>;
95 compatible = "st,stm32-timer-trigger";
102 #address-cells = <1>;
103 #size-cells = <0>;
104 compatible = "st,stm32-timers";
106 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
107 clock-names = "int";
111 compatible = "st,stm32-pwm";
112 #pwm-cells = <3>;
117 compatible = "st,stm32-timer-trigger";
124 #address-cells = <1>;
125 #size-cells = <0>;
126 compatible = "st,stm32-timers";
128 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
129 clock-names = "int";
133 compatible = "st,stm32-pwm";
134 #pwm-cells = <3>;
139 compatible = "st,stm32-timer-trigger";
146 #address-cells = <1>;
147 #size-cells = <0>;
148 compatible = "st,stm32-timers";
150 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
151 clock-names = "int";
155 compatible = "st,stm32-pwm";
156 #pwm-cells = <3>;
161 compatible = "st,stm32-timer-trigger";
168 #address-cells = <1>;
169 #size-cells = <0>;
170 compatible = "st,stm32-timers";
172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
173 clock-names = "int";
177 compatible = "st,stm32-timer-trigger";
184 #address-cells = <1>;
185 #size-cells = <0>;
186 compatible = "st,stm32-timers";
188 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
189 clock-names = "int";
193 compatible = "st,stm32-timer-trigger";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "st,stm32-timers";
204 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
205 clock-names = "int";
209 compatible = "st,stm32-pwm";
210 #pwm-cells = <3>;
215 compatible = "st,stm32-timer-trigger";
222 compatible = "st,stm32-timers";
224 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
225 clock-names = "int";
229 compatible = "st,stm32-pwm";
230 #pwm-cells = <3>;
236 compatible = "st,stm32-timers";
238 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
239 clock-names = "int";
243 compatible = "st,stm32-pwm";
244 #pwm-cells = <3>;
250 #address-cells = <1>;
251 #size-cells = <0>;
252 compatible = "st,stm32-lptimer";
254 interrupts-extended = <&exti 23 IRQ_TYPE_EDGE_RISING>;
255 clocks = <&rcc 1 CLK_LPTIMER>;
256 clock-names = "mux";
260 compatible = "st,stm32-pwm-lp";
261 #pwm-cells = <3>;
266 compatible = "st,stm32-lptimer-trigger";
272 compatible = "st,stm32-lptimer-counter";
277 compatible = "st,stm32-lptimer-timer";
283 compatible = "st,stm32-rtc";
285 clocks = <&rcc 1 CLK_RTC>;
286 assigned-clocks = <&rcc 1 CLK_RTC>;
287 assigned-clock-parents = <&rcc 1 CLK_LSE>;
288 interrupt-parent = <&exti>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 compatible = "st,stm32f7-spi";
300 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "st,stm32f7-spi";
310 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
315 compatible = "st,stm32f7-uart";
318 clocks = <&rcc 1 CLK_USART2>;
323 compatible = "st,stm32f7-uart";
326 clocks = <&rcc 1 CLK_USART3>;
331 compatible = "st,stm32f7-uart";
334 clocks = <&rcc 1 CLK_UART4>;
339 compatible = "st,stm32f7-uart";
342 clocks = <&rcc 1 CLK_UART5>;
347 compatible = "st,stm32f7-i2c";
351 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
352 clocks = <&rcc 1 CLK_I2C1>;
353 #address-cells = <1>;
354 #size-cells = <0>;
359 compatible = "st,stm32f7-i2c";
363 resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
364 clocks = <&rcc 1 CLK_I2C2>;
365 #address-cells = <1>;
366 #size-cells = <0>;
371 compatible = "st,stm32f7-i2c";
375 resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
376 clocks = <&rcc 1 CLK_I2C3>;
377 #address-cells = <1>;
378 #size-cells = <0>;
383 compatible = "st,stm32f7-i2c";
387 resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
388 clocks = <&rcc 1 CLK_I2C4>;
389 #address-cells = <1>;
390 #size-cells = <0>;
395 compatible = "st,stm32f4-bxcan";
398 interrupt-names = "tx", "rx0", "rx1", "sce";
399 resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
400 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
401 st,can-primary;
407 compatible = "st,stm32f4-gcan", "syscon";
409 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
413 compatible = "st,stm32f4-bxcan";
416 interrupt-names = "tx", "rx0", "rx1", "sce";
417 resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
418 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
419 st,can-secondary;
425 compatible = "st,stm32-cec";
428 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
429 clock-names = "cec", "hdmi-cec";
434 compatible = "st,stm32f7-uart";
437 clocks = <&rcc 1 CLK_UART7>;
442 compatible = "st,stm32f7-uart";
445 clocks = <&rcc 1 CLK_UART8>;
450 #address-cells = <1>;
451 #size-cells = <0>;
452 compatible = "st,stm32-timers";
454 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
455 clock-names = "int";
459 compatible = "st,stm32-pwm";
460 #pwm-cells = <3>;
465 compatible = "st,stm32-timer-trigger";
472 #address-cells = <1>;
473 #size-cells = <0>;
474 compatible = "st,stm32-timers";
476 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
477 clock-names = "int";
481 compatible = "st,stm32-pwm";
482 #pwm-cells = <3>;
487 compatible = "st,stm32-timer-trigger";
494 compatible = "st,stm32f7-uart";
497 clocks = <&rcc 1 CLK_USART1>;
502 compatible = "st,stm32f7-uart";
505 clocks = <&rcc 1 CLK_USART6>;
511 arm,primecell-periphid = <0x00880180>;
513 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
514 clock-names = "apb_pclk";
516 max-frequency = <48000000>;
522 arm,primecell-periphid = <0x00880180>;
524 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
525 clock-names = "apb_pclk";
527 max-frequency = <48000000>;
532 #address-cells = <1>;
533 #size-cells = <0>;
534 compatible = "st,stm32f7-spi";
537 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
542 #address-cells = <1>;
543 #size-cells = <0>;
544 compatible = "st,stm32f7-spi";
547 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
552 compatible = "st,stm32-syscfg", "syscon";
554 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>;
557 exti: interrupt-controller@40013c00 {
558 compatible = "st,stm32-exti";
559 interrupt-controller;
560 #interrupt-cells = <2>;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 compatible = "st,stm32-timers";
570 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
571 clock-names = "int";
575 compatible = "st,stm32-pwm";
576 #pwm-cells = <3>;
581 compatible = "st,stm32-timer-trigger";
588 compatible = "st,stm32-timers";
590 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
591 clock-names = "int";
595 compatible = "st,stm32-pwm";
596 #pwm-cells = <3>;
602 compatible = "st,stm32-timers";
604 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
605 clock-names = "int";
609 compatible = "st,stm32-pwm";
610 #pwm-cells = <3>;
616 #address-cells = <1>;
617 #size-cells = <0>;
618 compatible = "st,stm32f7-spi";
621 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
626 #address-cells = <1>;
627 #size-cells = <0>;
628 compatible = "st,stm32f7-spi";
631 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
635 ltdc: display-controller@40016800 {
636 compatible = "st,stm32-ltdc";
639 resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
640 clocks = <&rcc 1 CLK_LCD>;
641 clock-names = "lcd";
645 pwrcfg: power-config@40007000 {
646 compatible = "st,stm32-power-config", "syscon";
651 compatible = "st,stm32f7-crc";
653 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
657 rcc: rcc@40023800 { label
658 #reset-cells = <1>;
659 #clock-cells = <2>;
660 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
664 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
665 assigned-clock-rates = <1000000>;
668 dma1: dma-controller@40026000 {
669 compatible = "st,stm32-dma";
679 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
680 #dma-cells = <4>;
684 dma2: dma-controller@40026400 {
685 compatible = "st,stm32-dma";
695 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
696 #dma-cells = <4>;
702 compatible = "st,stm32f7-hsotg";
705 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
706 clock-names = "otg";
707 g-rx-fifo-size = <256>;
708 g-np-tx-fifo-size = <32>;
709 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
714 compatible = "st,stm32f4x9-fsotg";
717 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
718 clock-names = "otg";
725 clocks = <&rcc 1 0>;