Lines Matching full:rcc
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
84 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
106 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
128 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
150 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
188 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
204 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
224 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
238 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
255 clocks = <&rcc 1 CLK_LPTIMER>;
285 clocks = <&rcc 1 CLK_RTC>;
286 assigned-clocks = <&rcc 1 CLK_RTC>;
287 assigned-clock-parents = <&rcc 1 CLK_LSE>;
300 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
310 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
318 clocks = <&rcc 1 CLK_USART2>;
326 clocks = <&rcc 1 CLK_USART3>;
334 clocks = <&rcc 1 CLK_UART4>;
342 clocks = <&rcc 1 CLK_UART5>;
351 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
352 clocks = <&rcc 1 CLK_I2C1>;
363 resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
364 clocks = <&rcc 1 CLK_I2C2>;
375 resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
376 clocks = <&rcc 1 CLK_I2C3>;
387 resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
388 clocks = <&rcc 1 CLK_I2C4>;
399 resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
400 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
409 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
417 resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
418 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
428 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
437 clocks = <&rcc 1 CLK_UART7>;
445 clocks = <&rcc 1 CLK_UART8>;
454 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
476 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
497 clocks = <&rcc 1 CLK_USART1>;
505 clocks = <&rcc 1 CLK_USART6>;
513 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
524 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
537 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
547 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
554 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>;
570 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
590 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
604 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
621 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
631 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
639 resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
640 clocks = <&rcc 1 CLK_LCD>;
653 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
657 rcc: rcc@40023800 { label
660 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
664 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
679 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
695 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
705 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
717 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
725 clocks = <&rcc 1 0>;