Lines Matching +full:0 +full:x40026400
53 #clock-cells = <0>;
55 clock-frequency = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
80 #size-cells = <0>;
82 reg = <0x40000000 0x400>;
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
102 #size-cells = <0>;
104 reg = <0x40000400 0x400>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
124 #size-cells = <0>;
126 reg = <0x40000800 0x400>;
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
146 #size-cells = <0>;
148 reg = <0x40000C00 0x400>;
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
168 #size-cells = <0>;
170 reg = <0x40001000 0x400>;
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
184 #size-cells = <0>;
186 reg = <0x40001400 0x400>;
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
200 #size-cells = <0>;
202 reg = <0x40001800 0x400>;
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
222 reg = <0x40001C00 0x400>;
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
236 reg = <0x40002000 0x400>;
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
250 reg = <0x40002800 0x400>;
256 st,syscfg = <&pwrcfg 0x00 0x100>;
262 #size-cells = <0>;
264 reg = <0x40003800 0x400>;
266 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
272 #size-cells = <0>;
274 reg = <0x40003c00 0x400>;
276 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
282 reg = <0x40004400 0x400>;
290 reg = <0x40004800 0x400>;
298 reg = <0x40004c00 0x400>;
306 reg = <0x40005000 0x400>;
314 reg = <0x40005400 0x400>;
320 #size-cells = <0>;
326 reg = <0x40005800 0x400>;
332 #size-cells = <0>;
338 reg = <0x40005c00 0x400>;
344 #size-cells = <0>;
350 reg = <0x40006000 0x400>;
356 #size-cells = <0>;
362 reg = <0x40006400 0x200>;
366 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
374 reg = <0x40006600 0x200>;
375 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
380 reg = <0x40006800 0x200>;
384 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
392 reg = <0x40006C00 0x400>;
394 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
401 reg = <0x40007800 0x400>;
409 reg = <0x40007c00 0x400>;
417 #size-cells = <0>;
419 reg = <0x40010000 0x400>;
420 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
430 timer@0 {
432 reg = <0>;
439 #size-cells = <0>;
441 reg = <0x40010400 0x400>;
442 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
461 reg = <0x40011000 0x400>;
469 reg = <0x40011400 0x400>;
477 arm,primecell-periphid = <0x00880180>;
478 reg = <0x40011c00 0x400>;
479 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
488 arm,primecell-periphid = <0x00880180>;
489 reg = <0x40012c00 0x400>;
490 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
499 #size-cells = <0>;
501 reg = <0x40013000 0x400>;
503 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
509 #size-cells = <0>;
511 reg = <0x40013400 0x400>;
513 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
519 reg = <0x40013800 0x400>;
520 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>;
527 reg = <0x40013C00 0x400>;
533 #size-cells = <0>;
535 reg = <0x40014000 0x400>;
536 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
555 reg = <0x40014400 0x400>;
556 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
569 reg = <0x40014800 0x400>;
570 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
583 #size-cells = <0>;
585 reg = <0x40015000 0x400>;
587 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
593 #size-cells = <0>;
595 reg = <0x40015400 0x400>;
597 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
603 reg = <0x40016800 0x200>;
613 reg = <0x40007000 0x400>;
618 reg = <0x40023000 0x400>;
619 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
627 reg = <0x40023800 0x400>;
636 reg = <0x40026000 0x400>;
645 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
652 reg = <0x40026400 0x400>;
661 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
669 reg = <0x40040000 0x40000>;
671 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
681 reg = <0x50000000 0x40000>;
683 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
691 clocks = <&rcc 1 0>;