Lines Matching +full:i +full:- +full:drive
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
7 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
8 #include <dt-bindings/mfd/stm32f7-rcc.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 interrupt-parent = <&exti>;
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
26 st,bank-name = "GPIOA";
30 gpio-controller;
31 #gpio-cells = <2>;
32 interrupt-controller;
33 #interrupt-cells = <2>;
36 st,bank-name = "GPIOB";
40 gpio-controller;
41 #gpio-cells = <2>;
42 interrupt-controller;
43 #interrupt-cells = <2>;
46 st,bank-name = "GPIOC";
50 gpio-controller;
51 #gpio-cells = <2>;
52 interrupt-controller;
53 #interrupt-cells = <2>;
56 st,bank-name = "GPIOD";
60 gpio-controller;
61 #gpio-cells = <2>;
62 interrupt-controller;
63 #interrupt-cells = <2>;
66 st,bank-name = "GPIOE";
70 gpio-controller;
71 #gpio-cells = <2>;
72 interrupt-controller;
73 #interrupt-cells = <2>;
76 st,bank-name = "GPIOF";
80 gpio-controller;
81 #gpio-cells = <2>;
82 interrupt-controller;
83 #interrupt-cells = <2>;
86 st,bank-name = "GPIOG";
90 gpio-controller;
91 #gpio-cells = <2>;
92 interrupt-controller;
93 #interrupt-cells = <2>;
96 st,bank-name = "GPIOH";
100 gpio-controller;
101 #gpio-cells = <2>;
102 interrupt-controller;
103 #interrupt-cells = <2>;
106 st,bank-name = "GPIOI";
110 gpio-controller;
111 #gpio-cells = <2>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
116 st,bank-name = "GPIOJ";
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
126 st,bank-name = "GPIOK";
129 cec_pins_a: cec-0 {
132 slew-rate = <0>;
133 drive-open-drain;
134 bias-disable;
138 usart1_pins_a: usart1-0 {
141 bias-disable;
142 drive-push-pull;
143 slew-rate = <0>;
147 bias-disable;
151 usart1_pins_b: usart1-1 {
154 bias-disable;
155 drive-push-pull;
156 slew-rate = <0>;
160 bias-disable;
164 i2c1_pins_b: i2c1-0 {
168 bias-disable;
169 drive-open-drain;
170 slew-rate = <0>;
174 i2c3_pins_a: i2c3-0 {
178 bias-disable;
179 drive-open-drain;
180 slew-rate = <0>;
184 usbotg_hs_pins_a: usbotg-hs-0 {
187 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
198 bias-disable;
199 drive-push-pull;
200 slew-rate = <2>;
204 usbotg_hs_pins_b: usbotg-hs-1 {
218 bias-disable;
219 drive-push-pull;
220 slew-rate = <2>;
224 usbotg_fs_pins_a: usbotg-fs-0 {
229 bias-disable;
230 drive-push-pull;
231 slew-rate = <2>;
235 sdio_pins_a: sdio-pins-a-0 {
243 drive-push-pull;
244 slew-rate = <2>;
248 sdio_pins_od_a: sdio-pins-od-a-0 {
255 drive-push-pull;
256 slew-rate = <2>;
261 drive-open-drain;
262 slew-rate = <2>;
266 sdio_pins_sleep_a: sdio-pins-sleep-a-0 {
277 sdio_pins_b: sdio-pins-b-0 {
285 drive-push-pull;
286 slew-rate = <2>;
290 sdio_pins_od_b: sdio-pins-od-b-0 {
297 drive-push-pull;
298 slew-rate = <2>;
303 drive-open-drain;
304 slew-rate = <2>;
308 sdio_pins_sleep_b: sdio-pins-sleep-b-0 {
319 can1_pins_a: can1-0 {
325 bias-pull-up;
329 can1_pins_b: can1-1 {
335 bias-pull-up;
339 can1_pins_c: can1-2 {
345 bias-pull-up;
350 can1_pins_d: can1-3 {
356 bias-pull-up;
361 can2_pins_a: can2-0 {
367 bias-pull-up;
371 can2_pins_b: can2-1 {
377 bias-pull-up;
381 can3_pins_a: can3-0 {
387 bias-pull-up;
391 can3_pins_b: can3-1 {
397 bias-pull-up;
401 ltdc_pins_a: ltdc-0 {
405 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
406 <STM32_PINMUX('I',10, AF14)>, /* LCD_HSYNC */
407 <STM32_PINMUX('I',14, AF14)>, /* LCD_CLK */
408 <STM32_PINMUX('I',15, AF14)>, /* LCD_R0 */
431 slew-rate = <2>;