Lines Matching +full:stm32 +full:- +full:dcmi
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
63 clk_lse: clk-lse {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
69 clk_lsi: clk-lsi {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
75 clk_i2s_ckin: i2s-ckin {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
84 compatible = "st,stm32f4-otp";
86 #address-cells = <1>;
87 #size-cells = <1>;
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "st,stm32-timers";
102 clock-names = "int";
106 compatible = "st,stm32-pwm";
107 #pwm-cells = <3>;
112 compatible = "st,stm32-timer-trigger";
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "st,stm32-timers";
124 clock-names = "int";
128 compatible = "st,stm32-pwm";
129 #pwm-cells = <3>;
134 compatible = "st,stm32-timer-trigger";
141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "st,stm32-timers";
146 clock-names = "int";
150 compatible = "st,stm32-pwm";
151 #pwm-cells = <3>;
156 compatible = "st,stm32-timer-trigger";
163 #address-cells = <1>;
164 #size-cells = <0>;
165 compatible = "st,stm32-timers";
168 clock-names = "int";
172 compatible = "st,stm32-pwm";
173 #pwm-cells = <3>;
178 compatible = "st,stm32-timer-trigger";
185 #address-cells = <1>;
186 #size-cells = <0>;
187 compatible = "st,stm32-timers";
190 clock-names = "int";
194 compatible = "st,stm32-timer-trigger";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "st,stm32-timers";
206 clock-names = "int";
210 compatible = "st,stm32-timer-trigger";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "st,stm32-timers";
222 clock-names = "int";
226 compatible = "st,stm32-pwm";
227 #pwm-cells = <3>;
232 compatible = "st,stm32-timer-trigger";
239 compatible = "st,stm32-timers";
242 clock-names = "int";
246 compatible = "st,stm32-pwm";
247 #pwm-cells = <3>;
253 compatible = "st,stm32-timers";
256 clock-names = "int";
260 compatible = "st,stm32-pwm";
261 #pwm-cells = <3>;
267 compatible = "st,stm32-rtc";
270 assigned-clocks = <&rcc 1 CLK_RTC>;
271 assigned-clock-parents = <&rcc 1 CLK_LSE>;
272 interrupt-parent = <&exti>;
279 compatible = "st,stm32-iwdg";
282 clock-names = "lsi";
287 #address-cells = <1>;
288 #size-cells = <0>;
289 compatible = "st,stm32f4-spi";
297 #address-cells = <1>;
298 #size-cells = <0>;
299 compatible = "st,stm32f4-spi";
307 compatible = "st,stm32-uart";
315 compatible = "st,stm32-uart";
322 dma-names = "rx", "tx";
326 compatible = "st,stm32-uart";
334 compatible = "st,stm32-uart";
342 compatible = "st,stm32f4-i2c";
348 #address-cells = <1>;
349 #size-cells = <0>;
354 compatible = "st,stm32f4-i2c";
360 #address-cells = <1>;
361 #size-cells = <0>;
366 compatible = "st,stm32f4-bxcan";
369 interrupt-names = "tx", "rx0", "rx1", "sce";
372 st,can-primary;
378 compatible = "st,stm32f4-gcan", "syscon";
384 compatible = "st,stm32f4-bxcan";
387 interrupt-names = "tx", "rx0", "rx1", "sce";
390 st,can-secondary;
396 compatible = "st,stm32f4-dac-core";
400 clock-names = "pclk";
401 #address-cells = <1>;
402 #size-cells = <0>;
406 compatible = "st,stm32-dac";
407 #io-channel-cells = <1>;
413 compatible = "st,stm32-dac";
414 #io-channel-cells = <1>;
421 compatible = "st,stm32-uart";
429 compatible = "st,stm32-uart";
437 #address-cells = <1>;
438 #size-cells = <0>;
439 compatible = "st,stm32-timers";
442 clock-names = "int";
446 compatible = "st,stm32-pwm";
447 #pwm-cells = <3>;
452 compatible = "st,stm32-timer-trigger";
459 #address-cells = <1>;
460 #size-cells = <0>;
461 compatible = "st,stm32-timers";
464 clock-names = "int";
468 compatible = "st,stm32-pwm";
469 #pwm-cells = <3>;
474 compatible = "st,stm32-timer-trigger";
481 compatible = "st,stm32-uart";
488 dma-names = "rx", "tx";
492 compatible = "st,stm32-uart";
500 compatible = "st,stm32f4-adc-core";
504 clock-names = "adc";
505 interrupt-controller;
506 #interrupt-cells = <1>;
507 #address-cells = <1>;
508 #size-cells = <0>;
512 compatible = "st,stm32f4-adc";
513 #io-channel-cells = <1>;
516 interrupt-parent = <&adc>;
519 dma-names = "rx";
524 compatible = "st,stm32f4-adc";
525 #io-channel-cells = <1>;
528 interrupt-parent = <&adc>;
531 dma-names = "rx";
536 compatible = "st,stm32f4-adc";
537 #io-channel-cells = <1>;
540 interrupt-parent = <&adc>;
543 dma-names = "rx";
550 arm,primecell-periphid = <0x00880180>;
553 clock-names = "apb_pclk";
555 max-frequency = <48000000>;
560 #address-cells = <1>;
561 #size-cells = <0>;
562 compatible = "st,stm32f4-spi";
570 #address-cells = <1>;
571 #size-cells = <0>;
572 compatible = "st,stm32f4-spi";
580 compatible = "st,stm32-syscfg", "syscon";
585 exti: interrupt-controller@40013c00 {
586 compatible = "st,stm32-exti";
587 interrupt-controller;
588 #interrupt-cells = <2>;
594 #address-cells = <1>;
595 #size-cells = <0>;
596 compatible = "st,stm32-timers";
599 clock-names = "int";
603 compatible = "st,stm32-pwm";
604 #pwm-cells = <3>;
609 compatible = "st,stm32-timer-trigger";
616 compatible = "st,stm32-timers";
619 clock-names = "int";
623 compatible = "st,stm32-pwm";
624 #pwm-cells = <3>;
630 compatible = "st,stm32-timers";
633 clock-names = "int";
637 compatible = "st,stm32-pwm";
638 #pwm-cells = <3>;
644 #address-cells = <1>;
645 #size-cells = <0>;
646 compatible = "st,stm32f4-spi";
652 dma-names = "rx", "tx";
657 #address-cells = <1>;
658 #size-cells = <0>;
659 compatible = "st,stm32f4-spi";
666 pwrcfg: power-config@40007000 {
667 compatible = "st,stm32-power-config", "syscon";
671 ltdc: display-controller@40016800 {
672 compatible = "st,stm32-ltdc";
677 clock-names = "lcd";
682 compatible = "st,stm32f4-crc";
689 #reset-cells = <1>;
690 #clock-cells = <2>;
691 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
695 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
696 assigned-clock-rates = <1000000>;
699 dma1: dma-controller@40026000 {
700 compatible = "st,stm32-dma";
711 #dma-cells = <4>;
714 dma2: dma-controller@40026400 {
715 compatible = "st,stm32-dma";
726 #dma-cells = <4>;
731 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
733 reg-names = "stmmaceth";
735 interrupt-names = "macirq";
736 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
742 snps,mixed-burst;
747 compatible = "st,stm32-dma2d";
752 clock-names = "dma2d";
761 clock-names = "otg";
766 compatible = "st,stm32f4x9-fsotg";
770 clock-names = "otg";
774 dcmi: dcmi@50050000 { label
775 compatible = "st,stm32-dcmi";
778 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
779 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
780 clock-names = "mclk";
781 pinctrl-names = "default";
782 pinctrl-0 = <&dcmi_pins>;
784 dma-names = "tx";
789 compatible = "st,stm32-rng";