Lines Matching +full:rate +full:- +full:b
2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
21 * b) Permission is hereby granted, free of charge, to any person
43 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
44 #include <dt-bindings/mfd/stm32f4-rcc.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
52 interrupt-parent = <&exti>;
56 gpio-controller;
57 #gpio-cells = <2>;
58 interrupt-controller;
59 #interrupt-cells = <2>;
62 st,bank-name = "GPIOA";
66 gpio-controller;
67 #gpio-cells = <2>;
68 interrupt-controller;
69 #interrupt-cells = <2>;
72 st,bank-name = "GPIOB";
76 gpio-controller;
77 #gpio-cells = <2>;
78 interrupt-controller;
79 #interrupt-cells = <2>;
82 st,bank-name = "GPIOC";
86 gpio-controller;
87 #gpio-cells = <2>;
88 interrupt-controller;
89 #interrupt-cells = <2>;
92 st,bank-name = "GPIOD";
96 gpio-controller;
97 #gpio-cells = <2>;
98 interrupt-controller;
99 #interrupt-cells = <2>;
102 st,bank-name = "GPIOE";
106 gpio-controller;
107 #gpio-cells = <2>;
108 interrupt-controller;
109 #interrupt-cells = <2>;
112 st,bank-name = "GPIOF";
116 gpio-controller;
117 #gpio-cells = <2>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
122 st,bank-name = "GPIOG";
126 gpio-controller;
127 #gpio-cells = <2>;
128 interrupt-controller;
129 #interrupt-cells = <2>;
132 st,bank-name = "GPIOH";
136 gpio-controller;
137 #gpio-cells = <2>;
138 interrupt-controller;
139 #interrupt-cells = <2>;
142 st,bank-name = "GPIOI";
146 gpio-controller;
147 #gpio-cells = <2>;
148 interrupt-controller;
149 #interrupt-cells = <2>;
152 st,bank-name = "GPIOJ";
156 gpio-controller;
157 #gpio-cells = <2>;
158 interrupt-controller;
159 #interrupt-cells = <2>;
162 st,bank-name = "GPIOK";
165 usart1_pins_a: usart1-0 {
168 bias-disable;
169 drive-push-pull;
170 slew-rate = <0>;
174 bias-disable;
178 usart3_pins_a: usart3-0 {
180 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
181 bias-disable;
182 drive-push-pull;
183 slew-rate = <0>;
186 pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
187 bias-disable;
191 usbotg_fs_pins_a: usbotg-fs-0 {
196 bias-disable;
197 drive-push-pull;
198 slew-rate = <2>;
202 usbotg_fs_pins_b: usbotg-fs-1 {
204 pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
205 <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
206 <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
207 bias-disable;
208 drive-push-pull;
209 slew-rate = <2>;
213 usbotg_hs_pins_a: usbotg-hs-0 {
220 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
221 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
222 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
223 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
224 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
225 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
226 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
227 bias-disable;
228 drive-push-pull;
229 slew-rate = <2>;
233 ethernet_mii: mii-0 {
238 <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
249 slew-rate = <2>;
253 adc3_in8_pin: adc-200 {
259 pwm1_pins: pwm1-0 {
262 <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
263 <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
267 pwm3_pins: pwm3-0 {
269 pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
270 <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
274 i2c1_pins: i2c1-0 {
276 pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
277 <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
278 bias-disable;
279 drive-open-drain;
280 slew-rate = <3>;
284 ltdc_pins_a: ltdc-0 {
314 slew-rate = <2>;
318 ltdc_pins_b: ltdc-1 {
328 <STM32_PINMUX('B', 0, AF9)>,
334 <STM32_PINMUX('B', 1, AF9)>,
342 <STM32_PINMUX('B', 10, AF14)>,
348 <STM32_PINMUX('B', 11, AF14)>,
358 <STM32_PINMUX('B', 8, AF14)>,
360 <STM32_PINMUX('B', 9, AF14)>,
364 slew-rate = <2>;
368 spi5_pins: spi5-0 {
374 bias-disable;
375 drive-push-pull;
376 slew-rate = <0>;
381 bias-disable;
385 i2c3_pins: i2c3-0 {
391 bias-disable;
392 drive-open-drain;
393 slew-rate = <3>;
397 dcmi_pins: dcmi-0 {
400 <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
408 <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
414 bias-disable;
415 drive-push-pull;
416 slew-rate = <3>;
420 sdio_pins: sdio-pins-0 {
428 drive-push-pull;
429 slew-rate = <2>;
433 sdio_pins_od: sdio-pins-od-0 {
440 drive-push-pull;
441 slew-rate = <2>;
446 drive-open-drain;
447 slew-rate = <2>;
451 can1_pins_a: can1-0 {
453 pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
456 pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
457 bias-pull-up;
461 can2_pins_a: can2-0 {
463 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
466 pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
467 bias-pull-up;
471 can2_pins_b: can2-1 {
473 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
476 pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
477 bias-pull-up;