Lines Matching +full:0 +full:x10120000
14 reg = <0x00000000 0x04000000>,
15 <0x08000000 0x04000000>;
20 reg = <0x10210000 0x1000>;
37 reg = <0x101e2000 0x1000>;
46 reg = <0x101e3000 0x1000>;
55 reg = <0x101e4000 0x80>;
62 gpio-bank = <0>;
63 gpio-ranges = <&pinctrl 0 0 32>;
69 reg = <0x101e5000 0x80>;
77 gpio-ranges = <&pinctrl 0 32 32>;
83 reg = <0x101e6000 0x80>;
91 gpio-ranges = <&pinctrl 0 64 32>;
97 reg = <0x101e7000 0x80>;
106 gpio-ranges = <&pinctrl 0 96 28>;
133 * MCCMD, MCDAT3-0, MCMSFBCLK
152 ste,input = <0>;
166 ste,input = <0>;
187 reg = <0x101e0000 0x1000>;
192 reg = <0x101e0000 0x1000>;
199 #clock-cells = <0>;
211 #clock-cells = <0>;
219 pll1: pll1@0 {
220 #clock-cells = <0>;
227 hclk: hclk@0 {
228 #clock-cells = <0>;
233 pclk: pclk@0 {
234 #clock-cells = <0>;
242 pll2: pll2@0 {
243 #clock-cells = <0>;
249 #clock-cells = <0>;
256 #clock-cells = <0>;
263 #clock-cells = <0>;
271 #clock-cells = <0>;
279 #clock-cells = <0>;
288 #clock-cells = <0>;
299 #clock-cells = <0>;
301 clock-id = <0>;
305 #clock-cells = <0>;
311 #clock-cells = <0>;
317 #clock-cells = <0>;
323 #clock-cells = <0>;
329 #clock-cells = <0>;
335 #clock-cells = <0>;
341 #clock-cells = <0>;
347 #clock-cells = <0>;
353 #clock-cells = <0>;
359 #clock-cells = <0>;
365 #clock-cells = <0>;
371 #clock-cells = <0>;
377 #clock-cells = <0>;
383 #clock-cells = <0>;
389 #clock-cells = <0>;
395 #clock-cells = <0>;
401 #clock-cells = <0>;
407 #clock-cells = <0>;
413 #clock-cells = <0>;
419 #clock-cells = <0>;
425 #clock-cells = <0>;
431 #clock-cells = <0>;
437 #clock-cells = <0>;
443 #clock-cells = <0>;
449 #clock-cells = <0>;
455 #clock-cells = <0>;
461 #clock-cells = <0>;
467 #clock-cells = <0>;
473 #clock-cells = <0>;
479 #clock-cells = <0>;
485 #clock-cells = <0>;
492 clcdclk: clcdclk@0 {
493 #clock-cells = <0>;
499 #clock-cells = <0>;
505 #clock-cells = <0>;
511 #clock-cells = <0>;
518 #clock-cells = <0>;
524 #clock-cells = <0>;
530 #clock-cells = <0>;
536 #clock-cells = <0>;
542 #clock-cells = <0>;
548 #clock-cells = <0>;
554 #clock-cells = <0>;
560 #clock-cells = <0>;
566 #clock-cells = <0>;
572 #clock-cells = <0>;
578 #clock-cells = <0>;
584 #clock-cells = <0>;
590 #clock-cells = <0>;
596 #clock-cells = <0>;
602 #clock-cells = <0>;
608 #clock-cells = <0>;
614 #clock-cells = <0>;
620 #clock-cells = <0>;
626 #clock-cells = <0>;
632 #clock-cells = <0>;
638 #clock-cells = <0>;
645 #clock-cells = <0>;
657 reg = <0x10100000 0x1000>, /* FSMC Register*/
658 <0x40000000 0x2000>, /* NAND Base DATA */
659 <0x41000000 0x2000>, /* NAND Base ADDR */
660 <0x40800000 0x2000>; /* NAND Base CMD */
665 partition@0 {
667 reg = <0x0 0x40000>;
671 reg = <0x40000 0x40000>;
675 reg = <0x80000 0x200000>;
679 reg = <0x280000 0x300000>;
683 reg = <0x580000 0x1600000>;
687 reg = <0x1b80000 0x6480000>;
694 reg = <0x101f8000 0x1000>;
699 #size-cells = <0>;
703 pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>;
707 reg = <0x2d>;
720 reg = <0x101f7000 0x1000>;
725 #size-cells = <0>;
729 pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>;
733 reg = <0x10>;
737 reg = <0x1a>;
749 reg = <0x10120000 0x1000>;
762 reg = <0x10140000 0x20>;
769 reg = <0x10140020 0x20>;
774 reg = <0x101fd000 0x1000>;
787 reg = <0x101fb000 0x1000>;
793 pinctrl-0 = <&uart1_default_mux>;
801 reg = <0x101f2000 0x1000>;
814 reg = <0x101b0000 0x1000>;
821 reg = <0x101e8000 0x1000>;
830 reg = <0x101f6000 0x1000>;
851 pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
857 reg = <0x10130000 0x1000>;
871 reg = <0x10150000 0x1000>;