Lines Matching +full:uniphier +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro5 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "socionext,uniphier-pro5";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
24 enable-method = "psci";
25 next-level-cache = <&l2>;
26 operating-points-v2 = <&cpu_opp>;
31 compatible = "arm,cortex-a9";
34 enable-method = "psci";
35 next-level-cache = <&l2>;
36 operating-points-v2 = <&cpu_opp>;
40 cpu_opp: opp-table {
41 compatible = "operating-points-v2";
42 opp-shared;
44 opp-100000000 {
45 opp-hz = /bits/ 64 <100000000>;
46 clock-latency-ns = <300>;
48 opp-116667000 {
49 opp-hz = /bits/ 64 <116667000>;
50 clock-latency-ns = <300>;
52 opp-150000000 {
53 opp-hz = /bits/ 64 <150000000>;
54 clock-latency-ns = <300>;
56 opp-175000000 {
57 opp-hz = /bits/ 64 <175000000>;
58 clock-latency-ns = <300>;
60 opp-200000000 {
61 opp-hz = /bits/ 64 <200000000>;
62 clock-latency-ns = <300>;
64 opp-233334000 {
65 opp-hz = /bits/ 64 <233334000>;
66 clock-latency-ns = <300>;
68 opp-300000000 {
69 opp-hz = /bits/ 64 <300000000>;
70 clock-latency-ns = <300>;
72 opp-350000000 {
73 opp-hz = /bits/ 64 <350000000>;
74 clock-latency-ns = <300>;
76 opp-400000000 {
77 opp-hz = /bits/ 64 <400000000>;
78 clock-latency-ns = <300>;
80 opp-466667000 {
81 opp-hz = /bits/ 64 <466667000>;
82 clock-latency-ns = <300>;
84 opp-600000000 {
85 opp-hz = /bits/ 64 <600000000>;
86 clock-latency-ns = <300>;
88 opp-700000000 {
89 opp-hz = /bits/ 64 <700000000>;
90 clock-latency-ns = <300>;
92 opp-800000000 {
93 opp-hz = /bits/ 64 <800000000>;
94 clock-latency-ns = <300>;
96 opp-933334000 {
97 opp-hz = /bits/ 64 <933334000>;
98 clock-latency-ns = <300>;
100 opp-1200000000 {
101 opp-hz = /bits/ 64 <1200000000>;
102 clock-latency-ns = <300>;
104 opp-1400000000 {
105 opp-hz = /bits/ 64 <1400000000>;
106 clock-latency-ns = <300>;
111 compatible = "arm,psci-0.2";
117 compatible = "fixed-clock";
118 #clock-cells = <0>;
119 clock-frequency = <20000000>;
122 arm_timer_clk: arm-timer {
123 #clock-cells = <0>;
124 compatible = "fixed-clock";
125 clock-frequency = <50000000>;
130 compatible = "simple-bus";
131 #address-cells = <1>;
132 #size-cells = <1>;
134 interrupt-parent = <&intc>;
136 l2: cache-controller@500c0000 {
137 compatible = "socionext,uniphier-system-cache";
142 cache-unified;
143 cache-size = <(2 * 1024 * 1024)>;
144 cache-sets = <512>;
145 cache-line-size = <128>;
146 cache-level = <2>;
147 next-level-cache = <&l3>;
150 l3: cache-controller@500c8000 {
151 compatible = "socionext,uniphier-system-cache";
156 cache-unified;
157 cache-size = <(2 * 1024 * 1024)>;
158 cache-sets = <512>;
159 cache-line-size = <256>;
160 cache-level = <3>;
164 compatible = "socionext,uniphier-scssi";
167 #address-cells = <1>;
168 #size-cells = <0>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_spi0>;
177 compatible = "socionext,uniphier-scssi";
180 #address-cells = <1>;
181 #size-cells = <0>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_spi1>;
190 compatible = "socionext,uniphier-uart";
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_uart0>;
201 compatible = "socionext,uniphier-uart";
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_uart1>;
212 compatible = "socionext,uniphier-uart";
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_uart2>;
223 compatible = "socionext,uniphier-uart";
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_uart3>;
234 compatible = "socionext,uniphier-gpio";
236 interrupt-parent = <&aidet>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 gpio-controller;
240 #gpio-cells = <2>;
241 gpio-ranges = <&pinctrl 0 0 0>;
242 gpio-ranges-group-names = "gpio_range";
244 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
248 compatible = "socionext,uniphier-fi2c";
251 #address-cells = <1>;
252 #size-cells = <0>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_i2c0>;
258 clock-frequency = <100000>;
262 compatible = "socionext,uniphier-fi2c";
265 #address-cells = <1>;
266 #size-cells = <0>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_i2c1>;
272 clock-frequency = <100000>;
276 compatible = "socionext,uniphier-fi2c";
279 #address-cells = <1>;
280 #size-cells = <0>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_i2c2>;
286 clock-frequency = <100000>;
290 compatible = "socionext,uniphier-fi2c";
293 #address-cells = <1>;
294 #size-cells = <0>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_i2c3>;
300 clock-frequency = <100000>;
305 /* chip-internal connection for DMD */
307 compatible = "socionext,uniphier-fi2c";
309 #address-cells = <1>;
310 #size-cells = <0>;
314 clock-frequency = <400000>;
317 /* chip-internal connection for HDMI */
319 compatible = "socionext,uniphier-fi2c";
321 #address-cells = <1>;
322 #size-cells = <0>;
326 clock-frequency = <400000>;
329 system_bus: system-bus@58c00000 {
330 compatible = "socionext,uniphier-system-bus";
333 #address-cells = <2>;
334 #size-cells = <1>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_system_bus>;
340 compatible = "socionext,uniphier-smpctrl";
345 compatible = "socionext,uniphier-pro5-sdctrl",
346 "simple-mfd", "syscon";
349 sd_clk: clock-controller {
350 compatible = "socionext,uniphier-pro5-sd-clock";
351 #clock-cells = <1>;
354 sd_rst: reset-controller {
355 compatible = "socionext,uniphier-pro5-sd-reset";
356 #reset-cells = <1>;
361 compatible = "socionext,uniphier-pro5-perictrl",
362 "simple-mfd", "syscon";
365 peri_clk: clock-controller {
366 compatible = "socionext,uniphier-pro5-peri-clock";
367 #clock-cells = <1>;
370 peri_rst: reset-controller {
371 compatible = "socionext,uniphier-pro5-peri-reset";
372 #reset-cells = <1>;
377 compatible = "socionext,uniphier-pro5-soc-glue",
378 "simple-mfd", "syscon";
382 compatible = "socionext,uniphier-pro5-pinctrl";
387 compatible = "socionext,uniphier-pro5-soc-glue-debug",
388 "simple-mfd", "syscon";
390 #address-cells = <1>;
391 #size-cells = <1>;
395 compatible = "socionext,uniphier-efuse";
400 compatible = "socionext,uniphier-efuse";
405 compatible = "socionext,uniphier-efuse";
410 compatible = "socionext,uniphier-efuse";
415 compatible = "socionext,uniphier-efuse";
420 xdmac: dma-controller@5fc10000 {
421 compatible = "socionext,uniphier-xdmac";
424 dma-channels = <16>;
425 #dma-cells = <2>;
428 aidet: interrupt-controller@5fc20000 {
429 compatible = "socionext,uniphier-pro5-aidet";
431 interrupt-controller;
432 #interrupt-cells = <2>;
436 compatible = "arm,cortex-a9-global-timer";
444 compatible = "arm,cortex-a9-twd-timer";
451 intc: interrupt-controller@60001000 {
452 compatible = "arm,cortex-a9-gic";
455 #interrupt-cells = <3>;
456 interrupt-controller;
460 compatible = "socionext,uniphier-pro5-sysctrl",
461 "simple-mfd", "syscon";
464 sys_clk: clock-controller {
465 compatible = "socionext,uniphier-pro5-clock";
466 #clock-cells = <1>;
469 sys_rst: reset-controller {
470 compatible = "socionext,uniphier-pro5-reset";
471 #reset-cells = <1>;
476 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
479 interrupt-names = "host";
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_usb0>;
483 clock-names = "ref", "bus_early", "suspend";
490 usb-controller@65b00000 {
491 compatible = "socionext,uniphier-pro5-dwc3-glue",
492 "simple-mfd";
494 #address-cells = <1>;
495 #size-cells = <1>;
498 usb0_rst: reset-controller@0 {
499 compatible = "socionext,uniphier-pro5-usb3-reset";
501 #reset-cells = <1>;
502 clock-names = "gio", "link";
504 reset-names = "gio", "link";
509 compatible = "socionext,uniphier-pro5-usb3-regulator";
511 clock-names = "gio", "link";
513 reset-names = "gio", "link";
518 compatible = "socionext,uniphier-pro5-usb3-hsphy";
520 #phy-cells = <0>;
521 clock-names = "gio", "link";
523 reset-names = "gio", "link";
525 vbus-supply = <&usb0_vbus0>;
529 compatible = "socionext,uniphier-pro5-usb3-ssphy";
531 #phy-cells = <0>;
532 clock-names = "gio", "link";
534 reset-names = "gio", "link";
536 vbus-supply = <&usb0_vbus0>;
541 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
544 interrupt-names = "host";
546 pinctrl-names = "default";
547 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
548 clock-names = "ref", "bus_early", "suspend";
555 usb-controller@65d00000 {
556 compatible = "socionext,uniphier-pro5-dwc3-glue",
557 "simple-mfd";
559 #address-cells = <1>;
560 #size-cells = <1>;
563 usb1_rst: reset-controller@0 {
564 compatible = "socionext,uniphier-pro5-usb3-reset";
566 #reset-cells = <1>;
567 clock-names = "gio", "link";
569 reset-names = "gio", "link";
574 compatible = "socionext,uniphier-pro5-usb3-regulator";
576 clock-names = "gio", "link";
578 reset-names = "gio", "link";
583 compatible = "socionext,uniphier-pro5-usb3-regulator";
585 clock-names = "gio", "link";
587 reset-names = "gio", "link";
592 compatible = "socionext,uniphier-pro5-usb3-hsphy";
594 #phy-cells = <0>;
595 clock-names = "gio", "link";
597 reset-names = "gio", "link";
599 vbus-supply = <&usb1_vbus0>;
603 compatible = "socionext,uniphier-pro5-usb3-hsphy";
605 #phy-cells = <0>;
606 clock-names = "gio", "link";
608 reset-names = "gio", "link";
610 vbus-supply = <&usb1_vbus1>;
614 compatible = "socionext,uniphier-pro5-usb3-ssphy";
616 #phy-cells = <0>;
617 clock-names = "gio", "link";
619 reset-names = "gio", "link";
621 vbus-supply = <&usb1_vbus0>;
625 pcie_ep: pcie-ep@66000000 {
626 compatible = "socionext,uniphier-pro5-pcie-ep";
628 reg-names = "dbi", "dbi2", "link", "addr_space";
631 pinctrl-names = "default";
632 pinctrl-0 = <&pinctrl_pcie>;
633 clock-names = "gio", "link";
635 reset-names = "gio", "link";
637 num-ib-windows = <16>;
638 num-ob-windows = <16>;
639 num-lanes = <4>;
640 phy-names = "pcie-phy";
645 compatible = "socionext,uniphier-pro5-pcie-phy";
647 #phy-cells = <0>;
648 clock-names = "gio", "link";
650 reset-names = "gio", "link";
654 nand: nand-controller@68000000 {
655 compatible = "socionext,uniphier-denali-nand-v5b";
657 reg-names = "nand_data", "denali_reg";
659 #address-cells = <1>;
660 #size-cells = <0>;
662 pinctrl-names = "default";
663 pinctrl-0 = <&pinctrl_nand>;
664 clock-names = "nand", "nand_x", "ecc";
666 reset-names = "nand", "reg";
671 compatible = "socionext,uniphier-sd-v3.1";
675 pinctrl-names = "default";
676 pinctrl-0 = <&pinctrl_emmc>;
678 reset-names = "host", "hw";
680 bus-width = <8>;
681 cap-mmc-highspeed;
682 cap-mmc-hw-reset;
683 non-removable;
687 compatible = "socionext,uniphier-sd-v3.1";
691 pinctrl-names = "default", "uhs";
692 pinctrl-0 = <&pinctrl_sd>;
693 pinctrl-1 = <&pinctrl_sd_uhs>;
695 reset-names = "host";
697 bus-width = <4>;
698 cap-sd-highspeed;
699 sd-uhs-sdr12;
700 sd-uhs-sdr25;
701 sd-uhs-sdr50;
702 socionext,syscon-uhs-mode = <&sdctrl 0>;
707 #include "uniphier-pinctrl.dtsi"