Lines Matching +full:0 +full:x10060000
153 cluster_a15_opp_table: opp-table-0 {
270 reg = <0x10d20000 0x1000>;
271 ranges = <0x0 0x10d20000 0x6000>;
276 reg = <0x4000 0x1000>;
281 reg = <0x5000 0x1000>;
287 reg = <0x10010000 0x30000>;
293 reg = <0x03810000 0x0c>;
303 reg = <0x11000000 0x10000>;
316 #size-cells = <0>;
317 reg = <0x12200000 0x2000>;
320 fifo-depth = <0x40>;
328 #size-cells = <0>;
329 reg = <0x12210000 0x2000>;
332 fifo-depth = <0x40>;
340 #size-cells = <0>;
341 reg = <0x12220000 0x1000>;
344 fifo-depth = <0x40>;
350 reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
373 reg = <0x10ca1000 0x200>;
379 reg = <0x10ca1400 0x200>;
385 reg = <0x10ca1800 0x200>;
391 reg = <0x10ca1c00 0x200>;
397 reg = <0x11a51000 0x200>;
403 reg = <0x11a51400 0x200>;
409 reg = <0x10d00000 0x2000>;
413 ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 {
414 event-name = "ppmu-event3-dmc0-0";
421 reg = <0x10d10000 0x2000>;
433 reg = <0x10d60000 0x2000>;
437 ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 {
438 event-name = "ppmu-event3-dmc1-0";
445 reg = <0x10d70000 0x2000>;
457 reg = <0x10044000 0x20>;
458 #power-domain-cells = <0>;
464 reg = <0x10044020 0x20>;
465 #power-domain-cells = <0>;
471 reg = <0x10044060 0x20>;
472 #power-domain-cells = <0>;
478 reg = <0x10044080 0x20>;
479 #power-domain-cells = <0>;
485 reg = <0x100440c0 0x20>;
486 #power-domain-cells = <0>;
492 reg = <0x100440e0 0x20>;
493 #power-domain-cells = <0>;
499 reg = <0x10044120 0x20>;
500 #power-domain-cells = <0>;
506 reg = <0x13400000 0x1000>;
518 reg = <0x13410000 0x1000>;
524 reg = <0x14000000 0x1000>;
530 reg = <0x14010000 0x1000>;
536 reg = <0x03860000 0x1000>;
543 reg = <0x03880000 0x1000>;
553 reg = <0x121a0000 0x1000>;
562 reg = <0x121b0000 0x1000>;
571 reg = <0x10800000 0x1000>;
580 reg = <0x11c10000 0x1000>;
597 reg = <0x03830000 0x100>;
598 dmas = <&adma 0>,
609 samsung,idma-addr = <0x03000000>;
611 pinctrl-0 = <&i2s0_bus>;
618 reg = <0x12d60000 0x100>;
628 pinctrl-0 = <&i2s1_bus>;
634 reg = <0x12d70000 0x100>;
644 pinctrl-0 = <&i2s2_bus>;
650 reg = <0x12d20000 0x100>;
656 #size-cells = <0>;
658 pinctrl-0 = <&spi0_bus>;
667 reg = <0x12d30000 0x100>;
673 #size-cells = <0>;
675 pinctrl-0 = <&spi1_bus>;
684 reg = <0x12d40000 0x100>;
690 #size-cells = <0>;
692 pinctrl-0 = <&spi2_bus>;
701 reg = <0x14500000 0x10000>;
708 #size-cells = <0>;
714 reg = <0x12e00000 0x1000>;
717 #size-cells = <0>;
719 pinctrl-0 = <&i2c8_hs_bus>;
727 reg = <0x12e10000 0x1000>;
730 #size-cells = <0>;
732 pinctrl-0 = <&i2c9_hs_bus>;
740 reg = <0x12e20000 0x1000>;
743 #size-cells = <0>;
745 pinctrl-0 = <&i2c10_hs_bus>;
753 reg = <0x14530000 0x70000>;
764 #sound-dai-cells = <0>;
768 reg = <0x145d0000 0x20>;
773 reg = <0x101b0000 0x200>;
780 pinctrl-0 = <&hdmi_cec>;
786 reg = <0x14450000 0x10000>;
798 reg = <0x11c00000 0x64>;
807 reg = <0x13e00000 0x1000>;
817 reg = <0x13e10000 0x1000>;
827 reg = <0x11800000 0x5000>;
877 reg = <0x12800000 0x1294>;
878 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
887 reg = <0x12810000 0x1294>;
888 interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
897 reg = <0x12820000 0x1294>;
898 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>;
907 reg = <0x11f50000 0x1000>;
916 reg = <0x11f60000 0x1000>;
925 reg = <0x10040000 0x5000>;
935 #phy-cells = <0>;
946 reg = <0x10060000 0x100>;
950 #thermal-sensor-cells = <0>;
955 reg = <0x10064000 0x100>;
959 #thermal-sensor-cells = <0>;
964 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
968 #thermal-sensor-cells = <0>;
973 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
977 #thermal-sensor-cells = <0>;
982 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
986 #thermal-sensor-cells = <0>;
991 reg = <0x10a60000 0x1000>;
996 #iommu-cells = <0>;
1001 reg = <0x10a70000 0x1000>;
1006 #iommu-cells = <0>;
1011 reg = <0x14650000 0x1000>;
1017 #iommu-cells = <0>;
1022 reg = <0x13e80000 0x1000>;
1024 interrupts = <2 0>;
1028 #iommu-cells = <0>;
1033 reg = <0x13e90000 0x1000>;
1039 #iommu-cells = <0>;
1044 reg = <0x12880000 0x1000>;
1050 #iommu-cells = <0>;
1055 reg = <0x12890000 0x1000>;
1060 #iommu-cells = <0>;
1065 reg = <0x128a0000 0x1000>;
1070 #iommu-cells = <0>;
1075 reg = <0x128c0000 0x1000>;
1081 #iommu-cells = <0>;
1086 reg = <0x128d0000 0x1000>;
1092 #iommu-cells = <0>;
1097 reg = <0x128e0000 0x1000>;
1103 #iommu-cells = <0>;
1108 reg = <0x11d40000 0x1000>;
1110 interrupts = <4 0>;
1113 #iommu-cells = <0>;
1118 reg = <0x11f10000 0x1000>;
1123 #iommu-cells = <0>;
1128 reg = <0x11f20000 0x1000>;
1132 #iommu-cells = <0>;
1137 reg = <0x11200000 0x1000>;
1143 #iommu-cells = <0>;
1148 reg = <0x11210000 0x1000>;
1154 #iommu-cells = <0>;
1159 reg = <0x14640000 0x1000>;
1165 #iommu-cells = <0>;
1170 reg = <0x14680000 0x1000>;
1172 interrupts = <3 0>;
1176 #iommu-cells = <0>;
1238 pinctrl-0 = <&i2c0_bus>;
1245 pinctrl-0 = <&i2c1_bus>;
1252 pinctrl-0 = <&i2c2_bus>;
1259 pinctrl-0 = <&i2c3_bus>;
1266 pinctrl-0 = <&i2c4_hs_bus>;
1273 pinctrl-0 = <&i2c5_hs_bus>;
1280 pinctrl-0 = <&i2c6_hs_bus>;
1287 pinctrl-0 = <&i2c7_hs_bus>;