Lines Matching +full:exynos5250 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5250 SoC device tree source
8 * Samsung Exynos5250 SoC device nodes are listed in this file.
9 * Exynos5250 based board files can include this file and provide
13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
17 #include <dt-bindings/clock/exynos5250.h>
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5250", "samsung,exynos5";
46 #address-cells = <1>;
47 #size-cells = <0>;
49 cpu-map {
62 compatible = "arm,cortex-a15";
64 clocks = <&clock CLK_ARM_CLK>;
65 clock-names = "cpu";
66 operating-points-v2 = <&cpu0_opp_table>;
67 #cooling-cells = <2>; /* min followed by max */
71 compatible = "arm,cortex-a15";
73 clocks = <&clock CLK_ARM_CLK>;
74 clock-names = "cpu";
75 operating-points-v2 = <&cpu0_opp_table>;
76 #cooling-cells = <2>; /* min followed by max */
80 cpu0_opp_table: opp-table-0 {
81 compatible = "operating-points-v2";
82 opp-shared;
84 opp-200000000 {
85 opp-hz = /bits/ 64 <200000000>;
86 opp-microvolt = <925000>;
87 clock-latency-ns = <140000>;
89 opp-300000000 {
90 opp-hz = /bits/ 64 <300000000>;
91 opp-microvolt = <937500>;
92 clock-latency-ns = <140000>;
94 opp-400000000 {
95 opp-hz = /bits/ 64 <400000000>;
96 opp-microvolt = <950000>;
97 clock-latency-ns = <140000>;
99 opp-500000000 {
100 opp-hz = /bits/ 64 <500000000>;
101 opp-microvolt = <975000>;
102 clock-latency-ns = <140000>;
104 opp-600000000 {
105 opp-hz = /bits/ 64 <600000000>;
106 opp-microvolt = <1000000>;
107 clock-latency-ns = <140000>;
109 opp-700000000 {
110 opp-hz = /bits/ 64 <700000000>;
111 opp-microvolt = <1012500>;
112 clock-latency-ns = <140000>;
114 opp-800000000 {
115 opp-hz = /bits/ 64 <800000000>;
116 opp-microvolt = <1025000>;
117 clock-latency-ns = <140000>;
119 opp-900000000 {
120 opp-hz = /bits/ 64 <900000000>;
121 opp-microvolt = <1050000>;
122 clock-latency-ns = <140000>;
124 opp-1000000000 {
125 opp-hz = /bits/ 64 <1000000000>;
126 opp-microvolt = <1075000>;
127 clock-latency-ns = <140000>;
128 opp-suspend;
130 opp-1100000000 {
131 opp-hz = /bits/ 64 <1100000000>;
132 opp-microvolt = <1100000>;
133 clock-latency-ns = <140000>;
135 opp-1200000000 {
136 opp-hz = /bits/ 64 <1200000000>;
137 opp-microvolt = <1125000>;
138 clock-latency-ns = <140000>;
140 opp-1300000000 {
141 opp-hz = /bits/ 64 <1300000000>;
142 opp-microvolt = <1150000>;
143 clock-latency-ns = <140000>;
145 opp-1400000000 {
146 opp-hz = /bits/ 64 <1400000000>;
147 opp-microvolt = <1200000>;
148 clock-latency-ns = <140000>;
150 opp-1500000000 {
151 opp-hz = /bits/ 64 <1500000000>;
152 opp-microvolt = <1225000>;
153 clock-latency-ns = <140000>;
155 opp-1600000000 {
156 opp-hz = /bits/ 64 <1600000000>;
157 opp-microvolt = <1250000>;
158 clock-latency-ns = <140000>;
160 opp-1700000000 {
161 opp-hz = /bits/ 64 <1700000000>;
162 opp-microvolt = <1300000>;
163 clock-latency-ns = <140000>;
168 compatible = "arm,cortex-a15-pmu";
169 interrupt-parent = <&combiner>;
175 compatible = "mmio-sram";
177 #address-cells = <1>;
178 #size-cells = <1>;
181 smp-sram@0 {
182 compatible = "samsung,exynos4210-sysram";
186 smp-sram@2f000 {
187 compatible = "samsung,exynos4210-sysram-ns";
192 pd_gsc: power-domain@10044000 {
193 compatible = "samsung,exynos4210-pd";
195 #power-domain-cells = <0>;
199 pd_mfc: power-domain@10044040 {
200 compatible = "samsung,exynos4210-pd";
202 #power-domain-cells = <0>;
206 pd_g3d: power-domain@10044060 {
207 compatible = "samsung,exynos4210-pd";
209 #power-domain-cells = <0>;
213 pd_disp1: power-domain@100440a0 {
214 compatible = "samsung,exynos4210-pd";
216 #power-domain-cells = <0>;
220 pd_mau: power-domain@100440c0 {
221 compatible = "samsung,exynos4210-pd";
223 #power-domain-cells = <0>;
227 clock: clock-controller@10010000 { label
228 compatible = "samsung,exynos5250-clock";
230 #clock-cells = <1>;
233 clock_audss: audss-clock-controller@3810000 {
234 compatible = "samsung,exynos5250-audss-clock";
236 #clock-cells = <1>;
237 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
238 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
239 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
240 power-domains = <&pd_mau>;
244 compatible = "samsung,exynos5250-mct",
245 "samsung,exynos4210-mct";
247 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
248 clock-names = "fin_pll", "mct";
249 interrupts-extended = <&combiner 23 3>,
258 compatible = "samsung,exynos5250-pinctrl";
262 wakup_eint: wakeup-interrupt-controller {
263 compatible = "samsung,exynos4210-wakeup-eint";
264 interrupt-parent = <&gic>;
270 compatible = "samsung,exynos5250-pinctrl";
276 compatible = "samsung,exynos5250-pinctrl";
282 compatible = "samsung,exynos5250-pinctrl";
285 power-domains = <&pd_mau>;
288 pmu_system_controller: system-controller@10040000 {
289 compatible = "samsung,exynos5250-pmu", "simple-mfd", "syscon";
291 clock-names = "clkout16";
292 clocks = <&clock CLK_FIN_PLL>;
293 #clock-cells = <1>;
294 interrupt-controller;
295 #interrupt-cells = <3>;
296 interrupt-parent = <&gic>;
298 dp_phy: dp-phy {
299 compatible = "samsung,exynos5250-dp-video-phy";
300 #phy-cells = <0>;
303 mipi_phy: mipi-phy {
304 compatible = "samsung,s5pv210-mipi-video-phy";
305 #phy-cells = <1>;
310 compatible = "samsung,exynos5250-wdt";
313 clocks = <&clock CLK_WDT>;
314 clock-names = "watchdog";
315 samsung,syscon-phandle = <&pmu_system_controller>;
319 compatible = "samsung,mfc-v6";
322 power-domains = <&pd_mfc>;
323 clocks = <&clock CLK_MFC>;
324 clock-names = "mfc";
326 iommu-names = "left", "right";
330 compatible = "samsung,exynos5250-rotator";
333 clocks = <&clock CLK_ROTATOR>;
334 clock-names = "rotator";
339 compatible = "samsung,exynos5250-mali", "arm,mali-t604";
344 interrupt-names = "job", "mmu", "gpu";
345 clocks = <&clock CLK_G3D>;
346 clock-names = "core";
347 operating-points-v2 = <&gpu_opp_table>;
348 power-domains = <&pd_g3d>;
351 gpu_opp_table: opp-table {
352 compatible = "operating-points-v2";
354 opp-100000000 {
355 opp-hz = /bits/ 64 <100000000>;
356 opp-microvolt = <925000>;
358 opp-160000000 {
359 opp-hz = /bits/ 64 <160000000>;
360 opp-microvolt = <925000>;
362 opp-266000000 {
363 opp-hz = /bits/ 64 <266000000>;
364 opp-microvolt = <1025000>;
366 opp-350000000 {
367 opp-hz = /bits/ 64 <350000000>;
368 opp-microvolt = <1075000>;
370 opp-400000000 {
371 opp-hz = /bits/ 64 <400000000>;
372 opp-microvolt = <1125000>;
374 opp-450000000 {
375 opp-hz = /bits/ 64 <450000000>;
376 opp-microvolt = <1150000>;
378 opp-533000000 {
379 opp-hz = /bits/ 64 <533000000>;
380 opp-microvolt = <1250000>;
386 compatible = "samsung,exynos5250-tmu";
389 clocks = <&clock CLK_TMU>;
390 clock-names = "tmu_apbif";
391 #thermal-sensor-cells = <0>;
395 compatible = "snps,dwc-ahci";
398 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
399 clock-names = "sata", "pclk";
401 phy-names = "sata-phy";
402 ports-implemented = <0x1>;
406 sata_phy: sata-phy@12170000 {
407 compatible = "samsung,exynos5250-sata-phy";
409 clocks = <&clock CLK_SATA_PHYCTRL>;
410 clock-names = "sata_phyctrl";
411 #phy-cells = <0>;
412 samsung,syscon-phandle = <&pmu_system_controller>;
416 /* i2c_0-3 are defined in exynos5.dtsi */
418 compatible = "samsung,s3c2440-i2c";
421 #address-cells = <1>;
422 #size-cells = <0>;
423 clocks = <&clock CLK_I2C4>;
424 clock-names = "i2c";
425 pinctrl-names = "default";
426 pinctrl-0 = <&i2c4_bus>;
431 compatible = "samsung,s3c2440-i2c";
434 #address-cells = <1>;
435 #size-cells = <0>;
436 clocks = <&clock CLK_I2C5>;
437 clock-names = "i2c";
438 pinctrl-names = "default";
439 pinctrl-0 = <&i2c5_bus>;
444 compatible = "samsung,s3c2440-i2c";
447 #address-cells = <1>;
448 #size-cells = <0>;
449 clocks = <&clock CLK_I2C6>;
450 clock-names = "i2c";
451 pinctrl-names = "default";
452 pinctrl-0 = <&i2c6_bus>;
457 compatible = "samsung,s3c2440-i2c";
460 #address-cells = <1>;
461 #size-cells = <0>;
462 clocks = <&clock CLK_I2C7>;
463 clock-names = "i2c";
464 pinctrl-names = "default";
465 pinctrl-0 = <&i2c7_bus>;
470 compatible = "samsung,s3c2440-hdmiphy-i2c";
473 #address-cells = <1>;
474 #size-cells = <0>;
475 clocks = <&clock CLK_I2C_HDMI>;
476 clock-names = "i2c";
479 hdmiphy: hdmi-phy@38 {
480 compatible = "samsung,exynos4212-hdmiphy";
486 compatible = "samsung,exynos5-sata-phy-i2c";
488 #address-cells = <1>;
489 #size-cells = <0>;
490 clocks = <&clock CLK_SATA_PHYI2C>;
491 clock-names = "i2c";
494 sata_phy_i2c: sata-phy-i2c@38 {
495 compatible = "samsung,exynos-sataphy-i2c";
502 compatible = "samsung,exynos4210-spi";
507 dma-names = "tx", "rx";
508 #address-cells = <1>;
509 #size-cells = <0>;
510 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
511 clock-names = "spi", "spi_busclk0";
512 pinctrl-names = "default";
513 pinctrl-0 = <&spi0_bus>;
514 fifo-depth = <256>;
518 compatible = "samsung,exynos4210-spi";
523 dma-names = "tx", "rx";
524 #address-cells = <1>;
525 #size-cells = <0>;
526 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
527 clock-names = "spi", "spi_busclk0";
528 pinctrl-names = "default";
529 pinctrl-0 = <&spi1_bus>;
530 fifo-depth = <64>;
534 compatible = "samsung,exynos4210-spi";
539 dma-names = "tx", "rx";
540 #address-cells = <1>;
541 #size-cells = <0>;
542 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
543 clock-names = "spi", "spi_busclk0";
544 pinctrl-names = "default";
545 pinctrl-0 = <&spi2_bus>;
546 fifo-depth = <64>;
550 compatible = "samsung,exynos5250-dw-mshc";
552 #address-cells = <1>;
553 #size-cells = <0>;
555 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
556 clock-names = "biu", "ciu";
557 fifo-depth = <0x80>;
562 compatible = "samsung,exynos5250-dw-mshc";
564 #address-cells = <1>;
565 #size-cells = <0>;
567 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
568 clock-names = "biu", "ciu";
569 fifo-depth = <0x80>;
574 compatible = "samsung,exynos5250-dw-mshc";
576 #address-cells = <1>;
577 #size-cells = <0>;
579 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
580 clock-names = "biu", "ciu";
581 fifo-depth = <0x80>;
586 compatible = "samsung,exynos5250-dw-mshc";
589 #address-cells = <1>;
590 #size-cells = <0>;
591 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
592 clock-names = "biu", "ciu";
593 fifo-depth = <0x80>;
598 compatible = "samsung,s5pv210-i2s";
604 dma-names = "tx", "rx", "tx-sec";
608 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
609 samsung,idma-addr = <0x03000000>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&i2s0_bus>;
612 power-domains = <&pd_mau>;
613 #clock-cells = <1>;
614 #sound-dai-cells = <1>;
618 compatible = "samsung,s3c6410-i2s";
623 dma-names = "tx", "rx";
624 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
625 clock-names = "iis", "i2s_opclk0";
626 pinctrl-names = "default";
627 pinctrl-0 = <&i2s1_bus>;
628 power-domains = <&pd_mau>;
629 #sound-dai-cells = <1>;
633 compatible = "samsung,s3c6410-i2s";
638 dma-names = "tx", "rx";
639 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
640 clock-names = "iis", "i2s_opclk0";
641 pinctrl-names = "default";
642 pinctrl-0 = <&i2s2_bus>;
643 power-domains = <&pd_mau>;
644 #sound-dai-cells = <1>;
648 compatible = "samsung,exynos5250-dwusb3";
649 clocks = <&clock CLK_USB3>;
650 clock-names = "usbdrd30";
651 #address-cells = <1>;
652 #size-cells = <1>;
660 phy-names = "usb2-phy", "usb3-phy";
665 compatible = "samsung,exynos5250-usbdrd-phy";
667 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
668 clock-names = "phy", "ref";
669 samsung,pmu-syscon = <&pmu_system_controller>;
670 #phy-cells = <1>;
674 compatible = "samsung,exynos4210-ehci";
678 clocks = <&clock CLK_USB2>;
679 clock-names = "usbhost";
681 phy-names = "host";
685 compatible = "samsung,exynos4210-ohci";
689 clocks = <&clock CLK_USB2>;
690 clock-names = "usbhost";
692 phy-names = "host";
696 compatible = "samsung,exynos5250-usb2-phy";
698 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
699 clock-names = "phy", "ref";
700 #phy-cells = <1>;
701 samsung,sysreg-phandle = <&sysreg_system_controller>;
702 samsung,pmureg-phandle = <&pmu_system_controller>;
705 pdma0: dma-controller@121a0000 {
709 clocks = <&clock CLK_PDMA0>;
710 clock-names = "apb_pclk";
711 #dma-cells = <1>;
714 pdma1: dma-controller@121b0000 {
718 clocks = <&clock CLK_PDMA1>;
719 clock-names = "apb_pclk";
720 #dma-cells = <1>;
723 mdma0: dma-controller@10800000 {
727 clocks = <&clock CLK_MDMA0>;
728 clock-names = "apb_pclk";
729 #dma-cells = <1>;
732 mdma1: dma-controller@11c10000 {
736 clocks = <&clock CLK_MDMA1>;
737 clock-names = "apb_pclk";
738 #dma-cells = <1>;
742 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
745 power-domains = <&pd_gsc>;
746 clocks = <&clock CLK_GSCL0>;
747 clock-names = "gscl";
752 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
755 power-domains = <&pd_gsc>;
756 clocks = <&clock CLK_GSCL1>;
757 clock-names = "gscl";
762 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
765 power-domains = <&pd_gsc>;
766 clocks = <&clock CLK_GSCL2>;
767 clock-names = "gscl";
772 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
775 power-domains = <&pd_gsc>;
776 clocks = <&clock CLK_GSCL3>;
777 clock-names = "gscl";
782 compatible = "samsung,exynos4212-hdmi";
784 power-domains = <&pd_disp1>;
786 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
787 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
788 <&clock CLK_MOUT_HDMI>;
789 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
791 samsung,syscon-phandle = <&pmu_system_controller>;
793 #sound-dai-cells = <0>;
798 compatible = "samsung,s5p-cec";
801 clocks = <&clock CLK_HDMI_CEC>;
802 clock-names = "hdmicec";
803 samsung,syscon-phandle = <&pmu_system_controller>;
804 hdmi-phandle = <&hdmi>;
805 pinctrl-names = "default";
806 pinctrl-0 = <&hdmi_cec>;
811 compatible = "samsung,exynos5250-mixer";
813 power-domains = <&pd_disp1>;
815 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
816 <&clock CLK_SCLK_HDMI>;
817 clock-names = "mixer", "hdmi", "sclk_hdmi";
823 compatible = "samsung,exynos4210-mipi-dsi";
826 samsung,power-domain = <&pd_disp1>;
828 phy-names = "dsim";
829 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
830 clock-names = "bus_clk", "sclk_mipi";
832 #address-cells = <1>;
833 #size-cells = <0>;
837 compatible = "samsung,exynos-adc-v1";
840 clocks = <&clock CLK_ADC>;
841 clock-names = "adc";
842 #io-channel-cells = <1>;
843 samsung,syscon-phandle = <&pmu_system_controller>;
848 compatible = "samsung,exynos-sysmmu";
850 interrupt-parent = <&combiner>;
852 clock-names = "sysmmu", "master";
853 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
854 #iommu-cells = <0>;
858 compatible = "samsung,exynos-sysmmu";
860 interrupt-parent = <&combiner>;
862 power-domains = <&pd_mfc>;
863 clock-names = "sysmmu", "master";
864 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
865 #iommu-cells = <0>;
869 compatible = "samsung,exynos-sysmmu";
871 interrupt-parent = <&combiner>;
873 power-domains = <&pd_mfc>;
874 clock-names = "sysmmu", "master";
875 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
876 #iommu-cells = <0>;
880 compatible = "samsung,exynos-sysmmu";
882 interrupt-parent = <&combiner>;
884 clock-names = "sysmmu", "master";
885 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
886 #iommu-cells = <0>;
890 compatible = "samsung,exynos-sysmmu";
892 interrupt-parent = <&combiner>;
894 power-domains = <&pd_gsc>;
895 clock-names = "sysmmu", "master";
896 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
897 #iommu-cells = <0>;
901 compatible = "samsung,exynos-sysmmu";
903 interrupt-parent = <&combiner>;
905 clock-names = "sysmmu";
906 clocks = <&clock CLK_SMMU_FIMC_ISP>;
907 #iommu-cells = <0>;
911 compatible = "samsung,exynos-sysmmu";
913 interrupt-parent = <&combiner>;
915 clock-names = "sysmmu";
916 clocks = <&clock CLK_SMMU_FIMC_DRC>;
917 #iommu-cells = <0>;
921 compatible = "samsung,exynos-sysmmu";
923 interrupt-parent = <&combiner>;
925 clock-names = "sysmmu";
926 clocks = <&clock CLK_SMMU_FIMC_FD>;
927 #iommu-cells = <0>;
931 compatible = "samsung,exynos-sysmmu";
933 interrupt-parent = <&combiner>;
935 clock-names = "sysmmu";
936 clocks = <&clock CLK_SMMU_FIMC_SCC>;
937 #iommu-cells = <0>;
941 compatible = "samsung,exynos-sysmmu";
943 interrupt-parent = <&combiner>;
945 clock-names = "sysmmu";
946 clocks = <&clock CLK_SMMU_FIMC_SCP>;
947 #iommu-cells = <0>;
951 compatible = "samsung,exynos-sysmmu";
953 interrupt-parent = <&combiner>;
955 clock-names = "sysmmu";
956 clocks = <&clock CLK_SMMU_FIMC_MCU>;
957 #iommu-cells = <0>;
961 compatible = "samsung,exynos-sysmmu";
963 interrupt-parent = <&combiner>;
965 clock-names = "sysmmu";
966 clocks = <&clock CLK_SMMU_FIMC_ODC>;
967 #iommu-cells = <0>;
971 compatible = "samsung,exynos-sysmmu";
973 interrupt-parent = <&combiner>;
975 clock-names = "sysmmu";
976 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
977 #iommu-cells = <0>;
981 compatible = "samsung,exynos-sysmmu";
983 interrupt-parent = <&combiner>;
985 clock-names = "sysmmu";
986 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
987 #iommu-cells = <0>;
991 compatible = "samsung,exynos-sysmmu";
993 interrupt-parent = <&combiner>;
995 clock-names = "sysmmu";
996 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
997 #iommu-cells = <0>;
1001 compatible = "samsung,exynos-sysmmu";
1003 interrupt-parent = <&combiner>;
1005 power-domains = <&pd_gsc>;
1006 clock-names = "sysmmu", "master";
1007 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
1008 #iommu-cells = <0>;
1012 compatible = "samsung,exynos-sysmmu";
1014 interrupt-parent = <&combiner>;
1016 power-domains = <&pd_gsc>;
1017 clock-names = "sysmmu", "master";
1018 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
1019 #iommu-cells = <0>;
1023 compatible = "samsung,exynos-sysmmu";
1025 interrupt-parent = <&combiner>;
1027 power-domains = <&pd_gsc>;
1028 clock-names = "sysmmu", "master";
1029 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1030 #iommu-cells = <0>;
1034 compatible = "samsung,exynos-sysmmu";
1036 interrupt-parent = <&combiner>;
1038 power-domains = <&pd_gsc>;
1039 clock-names = "sysmmu", "master";
1040 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1041 #iommu-cells = <0>;
1045 compatible = "samsung,exynos-sysmmu";
1047 interrupt-parent = <&combiner>;
1049 power-domains = <&pd_gsc>;
1050 clock-names = "sysmmu", "master";
1051 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1052 #iommu-cells = <0>;
1056 compatible = "samsung,exynos-sysmmu";
1058 interrupt-parent = <&combiner>;
1060 power-domains = <&pd_gsc>;
1061 clock-names = "sysmmu", "master";
1062 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1063 #iommu-cells = <0>;
1067 compatible = "samsung,exynos-sysmmu";
1069 interrupt-parent = <&combiner>;
1071 power-domains = <&pd_disp1>;
1072 clock-names = "sysmmu", "master";
1073 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1074 #iommu-cells = <0>;
1078 compatible = "samsung,exynos-sysmmu";
1080 interrupt-parent = <&combiner>;
1082 power-domains = <&pd_disp1>;
1083 clock-names = "sysmmu", "master";
1084 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1085 #iommu-cells = <0>;
1090 compatible = "arm,armv7-timer";
1097 * of U-Boot on Exynos don't set the CNTFRQ register,
1100 clock-frequency = <24000000>;
1105 polling-delay-passive = <0>;
1106 polling-delay = <0>;
1107 thermal-sensors = <&tmu>;
1109 cooling-maps {
1112 cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1116 cooling-device = <&cpu0 15 15>,
1123 power-domains = <&pd_disp1>;
1124 clocks = <&clock CLK_DP>;
1125 clock-names = "dp";
1127 phy-names = "dp";
1131 power-domains = <&pd_disp1>;
1132 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1133 clock-names = "sclk_fimd", "fimd";
1139 clocks = <&clock CLK_G2D>;
1140 clock-names = "fimg2d";
1145 clocks = <&clock CLK_I2C0>;
1146 clock-names = "i2c";
1147 pinctrl-names = "default";
1148 pinctrl-0 = <&i2c0_bus>;
1152 clocks = <&clock CLK_I2C1>;
1153 clock-names = "i2c";
1154 pinctrl-names = "default";
1155 pinctrl-0 = <&i2c1_bus>;
1159 clocks = <&clock CLK_I2C2>;
1160 clock-names = "i2c";
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&i2c2_bus>;
1166 clocks = <&clock CLK_I2C3>;
1167 clock-names = "i2c";
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&i2c3_bus>;
1173 clocks = <&clock CLK_SSS>;
1174 clock-names = "secss";
1178 clocks = <&clock CLK_PWM>;
1179 clock-names = "timers";
1183 clocks = <&clock CLK_RTC>;
1184 clock-names = "rtc";
1185 interrupt-parent = <&pmu_system_controller>;
1190 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1191 clock-names = "uart", "clk_uart_baud0";
1193 dma-names = "rx", "tx";
1197 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1198 clock-names = "uart", "clk_uart_baud0";
1200 dma-names = "rx", "tx";
1204 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1205 clock-names = "uart", "clk_uart_baud0";
1207 dma-names = "rx", "tx";
1211 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1212 clock-names = "uart", "clk_uart_baud0";
1214 dma-names = "rx", "tx";
1218 clocks = <&clock CLK_SSS>;
1219 clock-names = "secss";
1223 clocks = <&clock CLK_SSS>;
1224 clock-names = "secss";
1227 #include "exynos5250-pinctrl.dtsi"
1228 #include "exynos-syscon-restart.dtsi"