Lines Matching +full:opp +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
41 opp-100000000 {
42 opp-hz = /bits/ 64 <100000000>;
44 opp-134000000 {
45 opp-hz = /bits/ 64 <134000000>;
47 opp-160000000 {
48 opp-hz = /bits/ 64 <160000000>;
50 opp-267000000 {
51 opp-hz = /bits/ 64 <267000000>;
56 bus_c2c: bus-c2c {
57 compatible = "samsung,exynos-bus";
59 clock-names = "bus";
60 operating-points-v2 = <&bus_dmc_opp_table>;
64 bus_dmc: bus-dmc {
65 compatible = "samsung,exynos-bus";
67 clock-names = "bus";
68 operating-points-v2 = <&bus_dmc_opp_table>;
69 samsung,data-clock-ratio = <4>;
70 #interconnect-cells = <0>;
74 bus_display: bus-display {
75 compatible = "samsung,exynos-bus";
77 clock-names = "bus";
78 operating-points-v2 = <&bus_display_opp_table>;
80 #interconnect-cells = <0>;
83 bus_display_opp_table: opp-table {
84 compatible = "operating-points-v2";
86 opp-160000000 {
87 opp-hz = /bits/ 64 <160000000>;
89 opp-200000000 {
90 opp-hz = /bits/ 64 <200000000>;
95 bus_fsys: bus-fsys {
96 compatible = "samsung,exynos-bus";
98 clock-names = "bus";
99 operating-points-v2 = <&bus_fsys_opp_table>;
102 bus_fsys_opp_table: opp-table {
103 compatible = "operating-points-v2";
105 opp-100000000 {
106 opp-hz = /bits/ 64 <100000000>;
108 opp-134000000 {
109 opp-hz = /bits/ 64 <134000000>;
114 bus_leftbus: bus-leftbus {
115 compatible = "samsung,exynos-bus";
117 clock-names = "bus";
118 operating-points-v2 = <&bus_leftbus_opp_table>;
120 #interconnect-cells = <0>;
124 bus_mfc: bus-mfc {
125 compatible = "samsung,exynos-bus";
127 clock-names = "bus";
128 operating-points-v2 = <&bus_leftbus_opp_table>;
132 bus_peri: bus-peri {
133 compatible = "samsung,exynos-bus";
135 clock-names = "bus";
136 operating-points-v2 = <&bus_peri_opp_table>;
139 bus_peri_opp_table: opp-table {
140 compatible = "operating-points-v2";
142 opp-50000000 {
143 opp-hz = /bits/ 64 <50000000>;
145 opp-100000000 {
146 opp-hz = /bits/ 64 <100000000>;
151 bus_rightbus: bus-rightbus {
152 compatible = "samsung,exynos-bus";
154 clock-names = "bus";
155 operating-points-v2 = <&bus_leftbus_opp_table>;
159 bus_dmc_opp_table: opp-table-1 {
160 compatible = "operating-points-v2";
162 opp-100000000 {
163 opp-hz = /bits/ 64 <100000000>;
164 opp-microvolt = <900000>;
166 opp-134000000 {
167 opp-hz = /bits/ 64 <134000000>;
168 opp-microvolt = <900000>;
170 opp-160000000 {
171 opp-hz = /bits/ 64 <160000000>;
172 opp-microvolt = <900000>;
174 opp-267000000 {
175 opp-hz = /bits/ 64 <267000000>;
176 opp-microvolt = <950000>;
178 opp-400000000 {
179 opp-hz = /bits/ 64 <400000000>;
180 opp-microvolt = <1050000>;
181 opp-suspend;
185 bus_leftbus_opp_table: opp-table-2 {
186 compatible = "operating-points-v2";
188 opp-100000000 {
189 opp-hz = /bits/ 64 <100000000>;
190 opp-microvolt = <900000>;
192 opp-134000000 {
193 opp-hz = /bits/ 64 <134000000>;
194 opp-microvolt = <925000>;
196 opp-160000000 {
197 opp-hz = /bits/ 64 <160000000>;
198 opp-microvolt = <950000>;
200 opp-200000000 {
201 opp-hz = /bits/ 64 <200000000>;
202 opp-microvolt = <1000000>;
203 opp-suspend;
210 compatible = "samsung,exynos4x12-pinctrl";
211 reg = <0x11400000 0x1000>;
216 compatible = "samsung,exynos4x12-pinctrl";
217 reg = <0x11000000 0x1000>;
220 wakup_eint: wakeup-interrupt-controller {
221 compatible = "samsung,exynos4210-wakeup-eint";
222 interrupt-parent = <&gic>;
228 compatible = "samsung,exynos4x12-pinctrl";
229 reg = <0x03860000 0x1000>;
230 interrupt-parent = <&combiner>;
231 interrupts = <10 0>;
235 compatible = "samsung,exynos4x12-pinctrl";
236 reg = <0x106e0000 0x1000>;
241 compatible = "mmio-sram";
242 reg = <0x02020000 0x40000>;
243 #address-cells = <1>;
244 #size-cells = <1>;
245 ranges = <0 0x02020000 0x40000>;
247 smp-sram@0 {
248 compatible = "samsung,exynos4210-sysram";
249 reg = <0x0 0x1000>;
252 smp-sram@2f000 {
253 compatible = "samsung,exynos4210-sysram-ns";
254 reg = <0x2f000 0x1000>;
258 pd_isp: power-domain@10023ca0 {
259 compatible = "samsung,exynos4210-pd";
260 reg = <0x10023ca0 0x20>;
261 #power-domain-cells = <0>;
265 l2c: cache-controller@10502000 {
266 compatible = "arm,pl310-cache";
267 reg = <0x10502000 0x1000>;
268 cache-unified;
269 cache-level = <2>;
270 prefetch-data = <1>;
271 prefetch-instr = <1>;
272 arm,tag-latency = <2 2 1>;
273 arm,data-latency = <3 2 1>;
274 arm,double-linefill = <1>;
275 arm,double-linefill-incr = <0>;
276 arm,double-linefill-wrap = <1>;
277 arm,prefetch-drop = <1>;
278 arm,prefetch-offset = <7>;
281 clock: clock-controller@10030000 {
282 reg = <0x10030000 0x18000>;
283 #clock-cells = <1>;
286 isp_clock: clock-controller@10048000 {
287 compatible = "samsung,exynos4412-isp-clock";
288 reg = <0x10048000 0x1000>;
289 #clock-cells = <1>;
290 power-domains = <&pd_isp>;
293 clock-names = "aclk200", "aclk400_mcuisp";
297 compatible = "samsung,exynos4412-mct";
298 reg = <0x10050000 0x800>;
300 clock-names = "fin_pll", "mct";
301 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
309 compatible = "samsung,exynos5250-wdt";
310 reg = <0x10060000 0x100>;
313 clock-names = "watchdog";
314 samsung,syscon-phandle = <&pmu_system_controller>;
318 compatible = "samsung,exynos4212-adc";
319 reg = <0x126c0000 0x100>;
320 interrupt-parent = <&combiner>;
323 clock-names = "adc";
324 #io-channel-cells = <1>;
325 samsung,syscon-phandle = <&pmu_system_controller>;
330 compatible = "samsung,exynos4212-g2d";
331 reg = <0x10800000 0x1000>;
334 clock-names = "sclk_fimg2d", "fimg2d";
339 compatible = "samsung,exynos4412-dw-mshc";
340 reg = <0x12550000 0x1000>;
342 #address-cells = <1>;
343 #size-cells = <0>;
344 fifo-depth = <0x80>;
346 clock-names = "biu", "ciu";
351 compatible = "samsung,exynos-sysmmu";
352 reg = <0x10a40000 0x1000>;
353 interrupt-parent = <&combiner>;
355 clock-names = "sysmmu", "master";
357 #iommu-cells = <0>;
361 compatible = "samsung,exynos-sysmmu";
362 reg = <0x12260000 0x1000>;
363 interrupt-parent = <&combiner>;
365 power-domains = <&pd_isp>;
366 clock-names = "sysmmu";
368 #iommu-cells = <0>;
372 compatible = "samsung,exynos-sysmmu";
373 reg = <0x12270000 0x1000>;
374 interrupt-parent = <&combiner>;
376 power-domains = <&pd_isp>;
377 clock-names = "sysmmu";
379 #iommu-cells = <0>;
383 compatible = "samsung,exynos-sysmmu";
384 reg = <0x122a0000 0x1000>;
385 interrupt-parent = <&combiner>;
387 power-domains = <&pd_isp>;
388 clock-names = "sysmmu";
390 #iommu-cells = <0>;
394 compatible = "samsung,exynos-sysmmu";
395 reg = <0x122b0000 0x1000>;
396 interrupt-parent = <&combiner>;
398 power-domains = <&pd_isp>;
399 clock-names = "sysmmu";
401 #iommu-cells = <0>;
405 compatible = "samsung,exynos-sysmmu";
406 reg = <0x123b0000 0x1000>;
407 interrupt-parent = <&combiner>;
408 interrupts = <16 0>;
409 power-domains = <&pd_isp>;
410 clock-names = "sysmmu", "master";
413 #iommu-cells = <0>;
417 compatible = "samsung,exynos-sysmmu";
418 reg = <0x123c0000 0x1000>;
419 interrupt-parent = <&combiner>;
421 power-domains = <&pd_isp>;
422 clock-names = "sysmmu", "master";
425 #iommu-cells = <0>;
431 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
454 ranges = <0x0 0x11800000 0xba1000>;
457 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
459 /* fimc_[0-3] are configured outside, under phandles */
460 fimc_lite_0: fimc-lite@b90000 {
461 compatible = "samsung,exynos4212-fimc-lite";
462 reg = <0x00b90000 0x1000>;
464 power-domains = <&pd_isp>;
466 clock-names = "flite";
471 fimc_lite_1: fimc-lite@ba0000 {
472 compatible = "samsung,exynos4212-fimc-lite";
473 reg = <0x00ba0000 0x1000>;
475 power-domains = <&pd_isp>;
477 clock-names = "flite";
482 fimc_is: fimc-is@800000 {
483 compatible = "samsung,exynos4212-fimc-is";
484 reg = <0x00800000 0x260000>;
487 power-domains = <&pd_isp>;
509 clock-names = "lite0", "lite1", "ppmuispx",
519 iommu-names = "isp", "drc", "fd", "mcuctl";
520 samsung,pmu-syscon = <&pmu_system_controller>;
521 #address-cells = <1>;
522 #size-cells = <1>;
526 i2c1_isp: i2c-isp@940000 {
527 compatible = "samsung,exynos4212-i2c-isp";
528 reg = <0x00940000 0x100>;
530 clock-names = "i2c_isp";
531 #address-cells = <1>;
532 #size-cells = <0>;
538 compatible = "samsung,exynos4x12-usb2-phy";
539 samsung,sysreg-phandle = <&sys_reg>;
543 compatible = "samsung,exynos4212-fimc";
544 samsung,pix-limits = <4224 8192 1920 4224>;
545 samsung,mainscaler-ext;
546 samsung,isp-wb;
547 samsung,cam-if;
551 compatible = "samsung,exynos4212-fimc";
552 samsung,pix-limits = <4224 8192 1920 4224>;
553 samsung,mainscaler-ext;
554 samsung,isp-wb;
555 samsung,cam-if;
559 compatible = "samsung,exynos4212-fimc";
560 samsung,pix-limits = <4224 8192 1920 4224>;
561 samsung,mainscaler-ext;
562 samsung,isp-wb;
563 samsung,lcd-wb;
564 samsung,cam-if;
568 compatible = "samsung,exynos4212-fimc";
569 samsung,pix-limits = <1920 8192 1366 1920>;
570 samsung,rotators = <0>;
571 samsung,mainscaler-ext;
572 samsung,isp-wb;
573 samsung,lcd-wb;
588 interrupt-names = "gp",
599 operating-points-v2 = <&gpu_opp_table>;
601 gpu_opp_table: opp-table {
602 compatible = "operating-points-v2";
604 opp-160000000 {
605 opp-hz = /bits/ 64 <160000000>;
606 opp-microvolt = <875000>;
608 opp-267000000 {
609 opp-hz = /bits/ 64 <267000000>;
610 opp-microvolt = <900000>;
612 opp-350000000 {
613 opp-hz = /bits/ 64 <350000000>;
614 opp-microvolt = <950000>;
616 opp-440000000 {
617 opp-hz = /bits/ 64 <440000000>;
618 opp-microvolt = <1025000>;
624 compatible = "samsung,exynos4212-hdmi";
628 compatible = "samsung,exynos4212-jpeg";
632 compatible = "samsung,exynos4212-rotator";
636 compatible = "samsung,exynos4212-mixer";
637 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
644 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
649 #clock-cells = <1>;
653 compatible = "samsung,exynos4412-tmu";
654 interrupt-parent = <&combiner>;
656 reg = <0x100c0000 0x100>;
658 clock-names = "tmu_apbif";
662 #include "exynos4x12-pinctrl.dtsi"