Lines Matching +full:smp +full:- +full:sram
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
40 opp-shared;
42 opp-134000000 {
43 opp-hz = /bits/ 64 <134000000>;
45 opp-160000000 {
46 opp-hz = /bits/ 64 <160000000>;
48 opp-200000000 {
49 opp-hz = /bits/ 64 <200000000>;
54 bus_display: bus-display {
55 compatible = "samsung,exynos-bus";
57 clock-names = "bus";
58 operating-points-v2 = <&bus_display_opp_table>;
61 bus_display_opp_table: opp-table {
62 compatible = "operating-points-v2";
63 opp-shared;
65 opp-100000000 {
66 opp-hz = /bits/ 64 <100000000>;
68 opp-134000000 {
69 opp-hz = /bits/ 64 <134000000>;
71 opp-160000000 {
72 opp-hz = /bits/ 64 <160000000>;
77 bus_dmc: bus-dmc {
78 compatible = "samsung,exynos-bus";
80 clock-names = "bus";
81 operating-points-v2 = <&bus_dmc_opp_table>;
84 bus_dmc_opp_table: opp-table {
85 compatible = "operating-points-v2";
86 opp-shared;
88 opp-134000000 {
89 opp-hz = /bits/ 64 <134000000>;
90 opp-microvolt = <1025000>;
92 opp-267000000 {
93 opp-hz = /bits/ 64 <267000000>;
94 opp-microvolt = <1050000>;
96 opp-400000000 {
97 opp-hz = /bits/ 64 <400000000>;
98 opp-microvolt = <1150000>;
99 opp-suspend;
104 bus_fsys: bus-fsys {
105 compatible = "samsung,exynos-bus";
107 clock-names = "bus";
108 operating-points-v2 = <&bus_fsys_opp_table>;
111 bus_fsys_opp_table: opp-table {
112 compatible = "operating-points-v2";
113 opp-shared;
115 opp-10000000 {
116 opp-hz = /bits/ 64 <10000000>;
118 opp-134000000 {
119 opp-hz = /bits/ 64 <134000000>;
124 bus_lcd0: bus-lcd0 {
125 compatible = "samsung,exynos-bus";
127 clock-names = "bus";
128 operating-points-v2 = <&bus_leftbus_opp_table>;
132 bus_leftbus: bus-leftbus {
133 compatible = "samsung,exynos-bus";
135 clock-names = "bus";
136 operating-points-v2 = <&bus_leftbus_opp_table>;
140 bus_mfc: bus-mfc {
141 compatible = "samsung,exynos-bus";
143 clock-names = "bus";
144 operating-points-v2 = <&bus_leftbus_opp_table>;
148 bus_peri: bus-peri {
149 compatible = "samsung,exynos-bus";
151 clock-names = "bus";
152 operating-points-v2 = <&bus_peri_opp_table>;
155 bus_peri_opp_table: opp-table {
156 compatible = "operating-points-v2";
157 opp-shared;
159 opp-5000000 {
160 opp-hz = /bits/ 64 <5000000>;
162 opp-100000000 {
163 opp-hz = /bits/ 64 <100000000>;
168 bus_rightbus: bus-rightbus {
169 compatible = "samsung,exynos-bus";
171 clock-names = "bus";
172 operating-points-v2 = <&bus_leftbus_opp_table>;
177 #address-cells = <1>;
178 #size-cells = <0>;
180 cpu-map {
193 compatible = "arm,cortex-a9";
196 clock-names = "cpu";
197 clock-latency = <160000>;
199 operating-points = <
207 #cooling-cells = <2>; /* min followed by max */
212 compatible = "arm,cortex-a9";
215 clock-names = "cpu";
216 clock-latency = <160000>;
218 operating-points = <
226 #cooling-cells = <2>; /* min followed by max */
230 bus_leftbus_opp_table: opp-table-0 {
231 compatible = "operating-points-v2";
232 opp-shared;
234 opp-100000000 {
235 opp-hz = /bits/ 64 <100000000>;
237 opp-160000000 {
238 opp-hz = /bits/ 64 <160000000>;
240 opp-200000000 {
241 opp-hz = /bits/ 64 <200000000>;
242 opp-suspend;
247 sysram: sram@2020000 {
248 compatible = "mmio-sram";
250 #address-cells = <1>;
251 #size-cells = <1>;
254 smp-sram@0 {
255 compatible = "samsung,exynos4210-sysram";
259 smp-sram@1f000 {
260 compatible = "samsung,exynos4210-sysram-ns";
265 pd_lcd1: power-domain@10023ca0 {
266 compatible = "samsung,exynos4210-pd";
268 #power-domain-cells = <0>;
272 l2c: cache-controller@10502000 {
273 compatible = "arm,pl310-cache";
275 cache-unified;
276 cache-level = <2>;
277 prefetch-data = <1>;
278 prefetch-instr = <1>;
279 arm,tag-latency = <2 2 1>;
280 arm,data-latency = <2 2 1>;
284 compatible = "samsung,exynos4210-mct";
287 clock-names = "fin_pll", "mct";
288 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
297 compatible = "samsung,s3c6410-wdt";
301 clock-names = "watchdog";
304 clock: clock-controller@10030000 {
305 compatible = "samsung,exynos4210-clock";
307 #clock-cells = <1>;
311 compatible = "samsung,exynos4210-pinctrl";
317 compatible = "samsung,exynos4210-pinctrl";
321 wakup_eint: wakeup-interrupt-controller {
322 compatible = "samsung,exynos4210-wakeup-eint";
323 interrupt-parent = <&gic>;
329 compatible = "samsung,exynos4210-pinctrl";
334 compatible = "samsung,s5pv210-g2d";
338 clock-names = "sclk_fimg2d", "fimg2d";
339 power-domains = <&pd_lcd0>;
344 compatible = "samsung,exynos-ppmu";
350 compatible = "samsung,exynos-ppmu";
353 clock-names = "ppmu";
358 compatible = "samsung,exynos-sysmmu";
360 interrupt-parent = <&combiner>;
362 clock-names = "sysmmu", "master";
364 power-domains = <&pd_lcd0>;
365 #iommu-cells = <0>;
369 compatible = "samsung,exynos-sysmmu";
370 interrupt-parent = <&combiner>;
373 clock-names = "sysmmu", "master";
375 power-domains = <&pd_lcd1>;
376 #iommu-cells = <0>;
402 polling-delay-passive = <5000>;
403 polling-delay = <5000>;
407 cpu-offset = <0x8000>;
413 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
417 samsung,combiner-nr = <16>;
437 samsung,pix-limits = <4224 8192 1920 4224>;
438 samsung,mainscaler-ext;
439 samsung,cam-if;
443 samsung,pix-limits = <4224 8192 1920 4224>;
444 samsung,mainscaler-ext;
445 samsung,cam-if;
449 samsung,pix-limits = <4224 8192 1920 4224>;
450 samsung,mainscaler-ext;
451 samsung,lcd-wb;
455 samsung,pix-limits = <1920 8192 1366 1920>;
457 samsung,mainscaler-ext;
458 samsung,lcd-wb;
472 interrupt-names = "gp",
482 operating-points-v2 = <&gpu_opp_table>;
484 gpu_opp_table: opp-table {
485 compatible = "operating-points-v2";
487 opp-160000000 {
488 opp-hz = /bits/ 64 <160000000>;
489 opp-microvolt = <950000>;
491 opp-267000000 {
492 opp-hz = /bits/ 64 <267000000>;
493 opp-microvolt = <1050000>;
499 power-domains = <&pd_lcd0>;
503 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
512 interrupt-affinity = <&cpu0>, <&cpu1>;
517 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
522 #clock-cells = <1>;
526 power-domains = <&pd_lcd0>;
530 power-domains = <&pd_lcd0>;
534 compatible = "samsung,exynos4210-tmu";
536 clock-names = "tmu_apbif";
539 #include "exynos4210-pinctrl.dtsi"