Lines Matching +full:pmu +full:- +full:sram
1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
46 bus_dmc: bus-dmc {
47 compatible = "samsung,exynos-bus";
49 clock-names = "bus";
50 operating-points-v2 = <&bus_dmc_opp_table>;
53 bus_dmc_opp_table: opp-table {
54 compatible = "operating-points-v2";
56 opp-50000000 {
57 opp-hz = /bits/ 64 <50000000>;
58 opp-microvolt = <800000>;
60 opp-100000000 {
61 opp-hz = /bits/ 64 <100000000>;
62 opp-microvolt = <800000>;
64 opp-134000000 {
65 opp-hz = /bits/ 64 <134000000>;
66 opp-microvolt = <800000>;
68 opp-200000000 {
69 opp-hz = /bits/ 64 <200000000>;
70 opp-microvolt = <825000>;
72 opp-400000000 {
73 opp-hz = /bits/ 64 <400000000>;
74 opp-microvolt = <875000>;
79 bus_fsys: bus-fsys {
80 compatible = "samsung,exynos-bus";
82 clock-names = "bus";
83 operating-points-v2 = <&bus_leftbus_opp_table>;
87 bus_isp: bus-isp {
88 compatible = "samsung,exynos-bus";
90 clock-names = "bus";
91 operating-points-v2 = <&bus_isp_opp_table>;
94 bus_isp_opp_table: opp-table {
95 compatible = "operating-points-v2";
97 opp-50000000 {
98 opp-hz = /bits/ 64 <50000000>;
100 opp-80000000 {
101 opp-hz = /bits/ 64 <80000000>;
103 opp-100000000 {
104 opp-hz = /bits/ 64 <100000000>;
106 opp-200000000 {
107 opp-hz = /bits/ 64 <200000000>;
109 opp-300000000 {
110 opp-hz = /bits/ 64 <300000000>;
115 bus_lcd0: bus-lcd0 {
116 compatible = "samsung,exynos-bus";
118 clock-names = "bus";
119 operating-points-v2 = <&bus_leftbus_opp_table>;
123 bus_leftbus: bus-leftbus {
124 compatible = "samsung,exynos-bus";
126 clock-names = "bus";
127 operating-points-v2 = <&bus_leftbus_opp_table>;
131 bus_mcuisp: bus-mcuisp {
132 compatible = "samsung,exynos-bus";
134 clock-names = "bus";
135 operating-points-v2 = <&bus_mcuisp_opp_table>;
138 bus_mcuisp_opp_table: opp-table {
139 compatible = "operating-points-v2";
141 opp-50000000 {
142 opp-hz = /bits/ 64 <50000000>;
144 opp-80000000 {
145 opp-hz = /bits/ 64 <80000000>;
147 opp-100000000 {
148 opp-hz = /bits/ 64 <100000000>;
150 opp-200000000 {
151 opp-hz = /bits/ 64 <200000000>;
153 opp-400000000 {
154 opp-hz = /bits/ 64 <400000000>;
159 bus_mfc: bus-mfc {
160 compatible = "samsung,exynos-bus";
162 clock-names = "bus";
163 operating-points-v2 = <&bus_leftbus_opp_table>;
167 bus_peril: bus-peril {
168 compatible = "samsung,exynos-bus";
170 clock-names = "bus";
171 operating-points-v2 = <&bus_peril_opp_table>;
174 bus_peril_opp_table: opp-table {
175 compatible = "operating-points-v2";
177 opp-50000000 {
178 opp-hz = /bits/ 64 <50000000>;
180 opp-80000000 {
181 opp-hz = /bits/ 64 <80000000>;
183 opp-100000000 {
184 opp-hz = /bits/ 64 <100000000>;
189 bus_rightbus: bus-rightbus {
190 compatible = "samsung,exynos-bus";
192 clock-names = "bus";
193 operating-points-v2 = <&bus_leftbus_opp_table>;
198 #address-cells = <1>;
199 #size-cells = <0>;
201 cpu-map {
214 compatible = "arm,cortex-a7";
216 clock-frequency = <1000000000>;
218 clock-names = "cpu";
219 #cooling-cells = <2>;
221 operating-points = <
237 compatible = "arm,cortex-a7";
239 clock-frequency = <1000000000>;
241 clock-names = "cpu";
242 #cooling-cells = <2>;
244 operating-points = <
259 xusbxti: clock-0 {
260 compatible = "fixed-clock";
261 clock-frequency = <0>;
262 #clock-cells = <0>;
263 clock-output-names = "xusbxti";
266 xxti: clock-1 {
267 compatible = "fixed-clock";
268 clock-frequency = <0>;
269 #clock-cells = <0>;
270 clock-output-names = "xxti";
273 xtcxo: clock-2 {
274 compatible = "fixed-clock";
275 clock-frequency = <0>;
276 #clock-cells = <0>;
277 clock-output-names = "xtcxo";
280 bus_leftbus_opp_table: opp-table-0 {
281 compatible = "operating-points-v2";
283 opp-50000000 {
284 opp-hz = /bits/ 64 <50000000>;
285 opp-microvolt = <900000>;
287 opp-80000000 {
288 opp-hz = /bits/ 64 <80000000>;
289 opp-microvolt = <900000>;
291 opp-100000000 {
292 opp-hz = /bits/ 64 <100000000>;
293 opp-microvolt = <1000000>;
295 opp-134000000 {
296 opp-hz = /bits/ 64 <134000000>;
297 opp-microvolt = <1000000>;
299 opp-200000000 {
300 opp-hz = /bits/ 64 <200000000>;
301 opp-microvolt = <1000000>;
305 pmu {
306 compatible = "arm,cortex-a7-pmu";
312 compatible = "simple-bus";
313 #address-cells = <1>;
314 #size-cells = <1>;
317 sram@2020000 {
318 compatible = "mmio-sram";
320 #address-cells = <1>;
321 #size-cells = <1>;
324 smp-sram@0 {
325 compatible = "samsung,exynos4210-sysram";
329 smp-sram@3f000 {
330 compatible = "samsung,exynos4210-sysram-ns";
336 compatible = "samsung,exynos4210-chipid";
341 compatible = "samsung,exynos3-sysreg", "syscon";
345 pmu_system_controller: system-controller@10020000 {
346 compatible = "samsung,exynos3250-pmu", "simple-mfd", "syscon";
348 interrupt-controller;
349 #interrupt-cells = <3>;
350 interrupt-parent = <&gic>;
351 clock-names = "clkout8";
353 #clock-cells = <1>;
355 mipi_phy: mipi-phy {
356 compatible = "samsung,s5pv210-mipi-video-phy";
357 #phy-cells = <1>;
361 pd_cam: power-domain@10023c00 {
362 compatible = "samsung,exynos4210-pd";
364 #power-domain-cells = <0>;
368 pd_mfc: power-domain@10023c40 {
369 compatible = "samsung,exynos4210-pd";
371 #power-domain-cells = <0>;
375 pd_g3d: power-domain@10023c60 {
376 compatible = "samsung,exynos4210-pd";
378 #power-domain-cells = <0>;
382 pd_lcd0: power-domain@10023c80 {
383 compatible = "samsung,exynos4210-pd";
385 #power-domain-cells = <0>;
389 pd_isp: power-domain@10023ca0 {
390 compatible = "samsung,exynos4210-pd";
392 #power-domain-cells = <0>;
396 cmu: clock-controller@10030000 {
397 compatible = "samsung,exynos3250-cmu";
399 #clock-cells = <1>;
400 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
402 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
406 cmu_dmc: clock-controller@105c0000 {
407 compatible = "samsung,exynos3250-cmu-dmc";
409 #clock-cells = <1>;
413 compatible = "samsung,s3c6410-rtc";
417 interrupt-parent = <&pmu_system_controller>;
422 compatible = "samsung,exynos3250-tmu";
426 clock-names = "tmu_apbif";
427 #thermal-sensor-cells = <0>;
431 gic: interrupt-controller@10481000 {
432 compatible = "arm,cortex-a15-gic";
433 #interrupt-cells = <3>;
434 interrupt-controller;
444 compatible = "samsung,exynos3250-mct",
445 "samsung,exynos4210-mct";
456 clock-names = "fin_pll", "mct";
460 compatible = "samsung,exynos3250-pinctrl";
464 wakeup-interrupt-controller {
465 compatible = "samsung,exynos4210-wakeup-eint";
471 compatible = "samsung,exynos3250-pinctrl";
477 compatible = "samsung,exynos3250-jpeg";
481 clock-names = "jpeg", "sclk";
482 power-domains = <&pd_cam>;
483 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
484 assigned-clock-rates = <0>, <150000000>;
485 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
491 compatible = "samsung,exynos-sysmmu";
494 clock-names = "sysmmu", "master";
496 power-domains = <&pd_cam>;
497 #iommu-cells = <0>;
501 compatible = "samsung,exynos3250-fimd";
503 interrupt-names = "fifo", "vsync", "lcd_sys";
508 clock-names = "sclk_fimd", "fimd";
509 power-domains = <&pd_lcd0>;
516 compatible = "samsung,exynos3250-mipi-dsi";
519 samsung,phy-type = <0>;
520 power-domains = <&pd_lcd0>;
522 phy-names = "dsim";
524 clock-names = "bus_clk", "pll_clk";
525 #address-cells = <1>;
526 #size-cells = <0>;
531 compatible = "samsung,exynos-sysmmu";
534 clock-names = "sysmmu", "master";
536 power-domains = <&pd_lcd0>;
537 #iommu-cells = <0>;
541 compatible = "samsung,s3c6400-hsotg";
545 clock-names = "otg";
547 phy-names = "usb2-phy";
552 compatible = "samsung,exynos5420-dw-mshc";
556 clock-names = "biu", "ciu";
557 fifo-depth = <0x80>;
558 #address-cells = <1>;
559 #size-cells = <0>;
564 compatible = "samsung,exynos5420-dw-mshc";
568 clock-names = "biu", "ciu";
569 fifo-depth = <0x80>;
570 #address-cells = <1>;
571 #size-cells = <0>;
576 compatible = "samsung,exynos5250-dw-mshc";
580 clock-names = "biu", "ciu";
581 fifo-depth = <0x80>;
582 #address-cells = <1>;
583 #size-cells = <0>;
587 exynos_usbphy: usb-phy@125b0000 {
588 compatible = "samsung,exynos3250-usb2-phy";
590 samsung,pmureg-phandle = <&pmu_system_controller>;
592 clock-names = "phy", "ref";
593 #phy-cells = <1>;
597 pdma0: dma-controller@12680000 {
602 clock-names = "apb_pclk";
603 #dma-cells = <1>;
606 pdma1: dma-controller@12690000 {
611 clock-names = "apb_pclk";
612 #dma-cells = <1>;
616 compatible = "samsung,exynos3250-adc";
619 clock-names = "adc", "sclk";
621 #io-channel-cells = <1>;
622 samsung,syscon-phandle = <&pmu_system_controller>;
627 compatible = "samsung,exynos4210-mali", "arm,mali-400";
640 interrupt-names = "gp",
650 "pmu";
653 clock-names = "bus", "core";
654 power-domains = <&pd_g3d>;
660 compatible = "samsung,exynos3250-mfc", "samsung,mfc-v7";
663 clock-names = "mfc", "sclk_mfc";
665 power-domains = <&pd_mfc>;
670 compatible = "samsung,exynos-sysmmu";
673 clock-names = "sysmmu", "master";
675 power-domains = <&pd_mfc>;
676 #iommu-cells = <0>;
680 compatible = "samsung,exynos4210-uart";
684 clock-names = "uart", "clk_uart_baud0";
685 pinctrl-names = "default";
686 pinctrl-0 = <&uart0_data &uart0_fctl>;
691 compatible = "samsung,exynos4210-uart";
695 clock-names = "uart", "clk_uart_baud0";
696 pinctrl-names = "default";
697 pinctrl-0 = <&uart1_data>;
702 compatible = "samsung,exynos4210-uart";
706 clock-names = "uart", "clk_uart_baud0";
707 pinctrl-names = "default";
708 pinctrl-0 = <&uart2_data>;
713 #address-cells = <1>;
714 #size-cells = <0>;
715 compatible = "samsung,s3c2440-i2c";
719 clock-names = "i2c";
720 pinctrl-names = "default";
721 pinctrl-0 = <&i2c0_bus>;
726 #address-cells = <1>;
727 #size-cells = <0>;
728 compatible = "samsung,s3c2440-i2c";
732 clock-names = "i2c";
733 pinctrl-names = "default";
734 pinctrl-0 = <&i2c1_bus>;
739 #address-cells = <1>;
740 #size-cells = <0>;
741 compatible = "samsung,s3c2440-i2c";
745 clock-names = "i2c";
746 pinctrl-names = "default";
747 pinctrl-0 = <&i2c2_bus>;
752 #address-cells = <1>;
753 #size-cells = <0>;
754 compatible = "samsung,s3c2440-i2c";
758 clock-names = "i2c";
759 pinctrl-names = "default";
760 pinctrl-0 = <&i2c3_bus>;
765 #address-cells = <1>;
766 #size-cells = <0>;
767 compatible = "samsung,s3c2440-i2c";
771 clock-names = "i2c";
772 pinctrl-names = "default";
773 pinctrl-0 = <&i2c4_bus>;
778 #address-cells = <1>;
779 #size-cells = <0>;
780 compatible = "samsung,s3c2440-i2c";
784 clock-names = "i2c";
785 pinctrl-names = "default";
786 pinctrl-0 = <&i2c5_bus>;
791 #address-cells = <1>;
792 #size-cells = <0>;
793 compatible = "samsung,s3c2440-i2c";
797 clock-names = "i2c";
798 pinctrl-names = "default";
799 pinctrl-0 = <&i2c6_bus>;
804 #address-cells = <1>;
805 #size-cells = <0>;
806 compatible = "samsung,s3c2440-i2c";
810 clock-names = "i2c";
811 pinctrl-names = "default";
812 pinctrl-0 = <&i2c7_bus>;
817 compatible = "samsung,exynos4210-spi";
821 dma-names = "tx", "rx";
822 #address-cells = <1>;
823 #size-cells = <0>;
825 clock-names = "spi", "spi_busclk0";
826 samsung,spi-src-clk = <0>;
827 pinctrl-names = "default";
828 pinctrl-0 = <&spi0_bus>;
829 fifo-depth = <256>;
834 compatible = "samsung,exynos4210-spi";
838 dma-names = "tx", "rx";
839 #address-cells = <1>;
840 #size-cells = <0>;
842 clock-names = "spi", "spi_busclk0";
843 samsung,spi-src-clk = <0>;
844 pinctrl-names = "default";
845 pinctrl-0 = <&spi1_bus>;
846 fifo-depth = <64>;
851 compatible = "samsung,s3c6410-i2s";
855 clock-names = "iis", "i2s_opclk0";
857 dma-names = "tx", "rx";
858 pinctrl-0 = <&i2s2_bus>;
859 pinctrl-names = "default";
864 compatible = "samsung,exynos4210-pwm";
871 #pwm-cells = <3>;
876 compatible = "samsung,exynos-ppmu";
882 compatible = "samsung,exynos-ppmu";
888 compatible = "samsung,exynos-ppmu";
894 compatible = "samsung,exynos-ppmu";
897 clock-names = "ppmu";
902 compatible = "samsung,exynos-ppmu";
905 clock-names = "ppmu";
910 compatible = "samsung,exynos-ppmu";
913 clock-names = "ppmu";
918 compatible = "samsung,exynos-ppmu";
921 clock-names = "ppmu";
926 compatible = "samsung,exynos-ppmu";
929 clock-names = "ppmu";
934 compatible = "samsung,exynos-ppmu";
937 clock-names = "ppmu";
942 compatible = "samsung,exynos-ppmu";
945 clock-names = "ppmu";
951 #include "exynos3250-pinctrl.dtsi"
952 #include "exynos-syscon-restart.dtsi"