Lines Matching +full:0 +full:x11c00000
199 #size-cells = <0>;
212 cpu0: cpu@0 {
215 reg = <0>;
259 xusbxti: clock-0 {
261 clock-frequency = <0>;
262 #clock-cells = <0>;
268 clock-frequency = <0>;
269 #clock-cells = <0>;
275 clock-frequency = <0>;
276 #clock-cells = <0>;
280 bus_leftbus_opp_table: opp-table-0 {
319 reg = <0x02020000 0x40000>;
322 ranges = <0 0x02020000 0x40000>;
324 smp-sram@0 {
326 reg = <0x0 0x1000>;
331 reg = <0x3f000 0x1000>;
337 reg = <0x10000000 0x100>;
342 reg = <0x10010000 0x400>;
347 reg = <0x10020000 0x4000>;
363 reg = <0x10023c00 0x20>;
364 #power-domain-cells = <0>;
370 reg = <0x10023c40 0x20>;
371 #power-domain-cells = <0>;
377 reg = <0x10023c60 0x20>;
378 #power-domain-cells = <0>;
384 reg = <0x10023c80 0x20>;
385 #power-domain-cells = <0>;
391 reg = <0x10023ca0 0x20>;
392 #power-domain-cells = <0>;
398 reg = <0x10030000 0x20000>;
408 reg = <0x105c0000 0x2000>;
414 reg = <0x10070000 0x100>;
423 reg = <0x100c0000 0x100>;
427 #thermal-sensor-cells = <0>;
435 reg = <0x10481000 0x1000>,
436 <0x10482000 0x2000>,
437 <0x10484000 0x2000>,
438 <0x10486000 0x2000>;
446 reg = <0x10050000 0x800>;
461 reg = <0x11000000 0x1000>;
472 reg = <0x11400000 0x1000>;
478 reg = <0x11830000 0x1000>;
484 assigned-clock-rates = <0>, <150000000>;
492 reg = <0x11a60000 0x1000>;
497 #iommu-cells = <0>;
502 reg = <0x11c00000 0x30000>;
517 reg = <0x11c80000 0x10000>;
519 samsung,phy-type = <0>;
526 #size-cells = <0>;
532 reg = <0x11e20000 0x1000>;
537 #iommu-cells = <0>;
542 reg = <0x12480000 0x20000>;
546 phys = <&exynos_usbphy 0>;
553 reg = <0x12510000 0x1000>;
557 fifo-depth = <0x80>;
559 #size-cells = <0>;
565 reg = <0x12520000 0x1000>;
569 fifo-depth = <0x80>;
571 #size-cells = <0>;
577 reg = <0x12530000 0x1000>;
581 fifo-depth = <0x80>;
583 #size-cells = <0>;
589 reg = <0x125b0000 0x100>;
599 reg = <0x12680000 0x1000>;
608 reg = <0x12690000 0x1000>;
617 reg = <0x126c0000 0x100>;
628 reg = <0x13000000 0x10000>;
661 reg = <0x13400000 0x10000>;
671 reg = <0x13620000 0x1000>;
676 #iommu-cells = <0>;
681 reg = <0x13800000 0x100>;
686 pinctrl-0 = <&uart0_data &uart0_fctl>;
692 reg = <0x13810000 0x100>;
697 pinctrl-0 = <&uart1_data>;
703 reg = <0x13820000 0x100>;
708 pinctrl-0 = <&uart2_data>;
714 #size-cells = <0>;
716 reg = <0x13860000 0x100>;
721 pinctrl-0 = <&i2c0_bus>;
727 #size-cells = <0>;
729 reg = <0x13870000 0x100>;
734 pinctrl-0 = <&i2c1_bus>;
740 #size-cells = <0>;
742 reg = <0x13880000 0x100>;
747 pinctrl-0 = <&i2c2_bus>;
753 #size-cells = <0>;
755 reg = <0x13890000 0x100>;
760 pinctrl-0 = <&i2c3_bus>;
766 #size-cells = <0>;
768 reg = <0x138a0000 0x100>;
773 pinctrl-0 = <&i2c4_bus>;
779 #size-cells = <0>;
781 reg = <0x138b0000 0x100>;
786 pinctrl-0 = <&i2c5_bus>;
792 #size-cells = <0>;
794 reg = <0x138c0000 0x100>;
799 pinctrl-0 = <&i2c6_bus>;
805 #size-cells = <0>;
807 reg = <0x138d0000 0x100>;
812 pinctrl-0 = <&i2c7_bus>;
818 reg = <0x13920000 0x100>;
823 #size-cells = <0>;
826 samsung,spi-src-clk = <0>;
828 pinctrl-0 = <&spi0_bus>;
835 reg = <0x13930000 0x100>;
840 #size-cells = <0>;
843 samsung,spi-src-clk = <0>;
845 pinctrl-0 = <&spi1_bus>;
852 reg = <0x13970000 0x100>;
858 pinctrl-0 = <&i2s2_bus>;
865 reg = <0x139d0000 0x1000>;
877 reg = <0x106a0000 0x2000>;
883 reg = <0x106b0000 0x2000>;
889 reg = <0x106c0000 0x2000>;
895 reg = <0x112a0000 0x2000>;
903 reg = <0x116a0000 0x2000>;
911 reg = <0x11ac0000 0x2000>;
919 reg = <0x11e40000 0x2000>;
927 reg = <0x12630000 0x2000>;
935 reg = <0x13220000 0x2000>;
943 reg = <0x13660000 0x2000>;