Lines Matching +full:rk3328 +full:- +full:cru
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
20 interrupt-parent = <&gic>;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a7";
42 enable-method = "psci";
43 clocks = <&cru ARMCLK>;
48 compatible = "arm,cortex-a7";
50 enable-method = "psci";
51 clocks = <&cru ARMCLK>;
56 compatible = "arm,cortex-a7";
58 enable-method = "psci";
59 clocks = <&cru ARMCLK>;
64 compatible = "arm,cortex-a7";
66 enable-method = "psci";
67 clocks = <&cru ARMCLK>;
71 arm-pmu {
72 compatible = "arm,cortex-a7-pmu";
77 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
81 compatible = "arm,psci-1.0";
86 compatible = "arm,armv7-timer";
91 clock-frequency = <24000000>;
95 compatible = "rockchip,display-subsystem";
100 compatible = "fixed-clock";
101 clock-frequency = <24000000>;
102 clock-output-names = "xin24m";
103 #clock-cells = <0>;
107 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
112 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
115 pmu_io_domains: io-domains {
116 compatible = "rockchip,rv1126-pmu-io-voltage-domain";
122 compatible = "rockchip,rv1126-qos", "syscon";
127 compatible = "rockchip,rv1126-qos", "syscon";
132 compatible = "rockchip,rv1126-qos", "syscon";
137 compatible = "rockchip,rv1126-qos", "syscon";
142 compatible = "rockchip,rv1126-qos", "syscon";
147 compatible = "rockchip,rv1126-qos", "syscon";
152 compatible = "rockchip,rv1126-qos", "syscon";
157 compatible = "rockchip,rv1126-qos", "syscon";
161 gic: interrupt-controller@feff0000 {
162 compatible = "arm,gic-400";
163 interrupt-controller;
164 #interrupt-cells = <3>;
165 #address-cells = <0>;
174 pmu: power-management@ff3e0000 {
175 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
178 power: power-controller {
179 compatible = "rockchip,rv1126-power-controller";
180 #power-domain-cells = <1>;
181 #address-cells = <1>;
182 #size-cells = <0>;
184 power-domain@RV1126_PD_NVM {
186 clocks = <&cru HCLK_EMMC>,
187 <&cru CLK_EMMC>,
188 <&cru HCLK_NANDC>,
189 <&cru CLK_NANDC>,
190 <&cru HCLK_SFC>,
191 <&cru HCLK_SFCXIP>,
192 <&cru SCLK_SFC>;
196 #power-domain-cells = <0>;
199 power-domain@RV1126_PD_SDIO {
201 clocks = <&cru HCLK_SDIO>,
202 <&cru CLK_SDIO>;
204 #power-domain-cells = <0>;
207 power-domain@RV1126_PD_VO {
209 clocks = <&cru ACLK_RGA>,
210 <&cru HCLK_RGA>,
211 <&cru CLK_RGA_CORE>,
212 <&cru ACLK_VOP>,
213 <&cru HCLK_VOP>,
214 <&cru DCLK_VOP>,
215 <&cru PCLK_DSIHOST>,
216 <&cru ACLK_IEP>,
217 <&cru HCLK_IEP>,
218 <&cru CLK_IEP_CORE>;
223 #power-domain-cells = <0>;
229 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
234 clock-names = "i2c", "pclk";
235 pinctrl-names = "default";
236 pinctrl-0 = <&i2c0_xfer>;
237 #address-cells = <1>;
238 #size-cells = <0>;
243 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
248 clock-names = "i2c", "pclk";
249 pinctrl-names = "default";
250 pinctrl-0 = <&i2c2_xfer>;
251 #address-cells = <1>;
252 #size-cells = <0>;
257 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
260 clock-frequency = <24000000>;
262 clock-names = "baudclk", "apb_pclk";
264 dma-names = "tx", "rx";
265 pinctrl-names = "default";
266 pinctrl-0 = <&uart1m0_xfer>;
267 reg-shift = <2>;
268 reg-io-width = <4>;
273 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
275 clock-names = "pwm", "pclk";
277 pinctrl-names = "default";
278 pinctrl-0 = <&pwm0m0_pins>;
279 #pwm-cells = <3>;
284 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
286 clock-names = "pwm", "pclk";
288 pinctrl-names = "default";
289 pinctrl-0 = <&pwm1m0_pins>;
290 #pwm-cells = <3>;
295 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
297 clock-names = "pwm", "pclk";
299 pinctrl-names = "default";
300 pinctrl-0 = <&pwm2m0_pins>;
301 #pwm-cells = <3>;
306 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
308 clock-names = "pwm", "pclk";
310 pinctrl-names = "default";
311 pinctrl-0 = <&pwm3m0_pins>;
312 #pwm-cells = <3>;
317 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
319 clock-names = "pwm", "pclk";
321 pinctrl-names = "default";
322 pinctrl-0 = <&pwm4m0_pins>;
323 #pwm-cells = <3>;
328 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
330 clock-names = "pwm", "pclk";
332 pinctrl-names = "default";
333 pinctrl-0 = <&pwm5m0_pins>;
334 #pwm-cells = <3>;
339 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
341 clock-names = "pwm", "pclk";
343 pinctrl-names = "default";
344 pinctrl-0 = <&pwm6m0_pins>;
345 #pwm-cells = <3>;
350 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
352 clock-names = "pwm", "pclk";
354 pinctrl-names = "default";
355 pinctrl-0 = <&pwm7m0_pins>;
356 #pwm-cells = <3>;
360 pmucru: clock-controller@ff480000 {
361 compatible = "rockchip,rv1126-pmucru";
364 #clock-cells = <1>;
365 #reset-cells = <1>;
368 cru: clock-controller@ff490000 { label
369 compatible = "rockchip,rv1126-cru";
372 clock-names = "xin24m";
374 #clock-cells = <1>;
375 #reset-cells = <1>;
378 dmac: dma-controller@ff4e0000 {
383 #dma-cells = <1>;
384 arm,pl330-periph-burst;
385 clocks = <&cru ACLK_DMAC>;
386 clock-names = "apb_pclk";
390 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
393 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
394 clock-names = "i2c", "pclk";
395 pinctrl-names = "default";
396 pinctrl-0 = <&i2c3m0_xfer>;
398 #address-cells = <1>;
399 #size-cells = <0>;
404 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
406 clock-names = "pwm", "pclk";
407 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
408 pinctrl-0 = <&pwm8m0_pins>;
409 pinctrl-names = "default";
410 #pwm-cells = <3>;
415 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
417 clock-names = "pwm", "pclk";
418 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
419 pinctrl-0 = <&pwm9m0_pins>;
420 pinctrl-names = "default";
421 #pwm-cells = <3>;
426 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
428 clock-names = "pwm", "pclk";
429 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
430 pinctrl-0 = <&pwm10m0_pins>;
431 pinctrl-names = "default";
432 #pwm-cells = <3>;
437 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
439 clock-names = "pwm", "pclk";
440 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
441 pinctrl-0 = <&pwm11m0_pins>;
442 pinctrl-names = "default";
443 #pwm-cells = <3>;
448 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
451 clock-frequency = <24000000>;
452 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
453 clock-names = "baudclk", "apb_pclk";
455 dma-names = "tx", "rx";
456 pinctrl-names = "default";
457 pinctrl-0 = <&uart0_xfer>;
458 reg-shift = <2>;
459 reg-io-width = <4>;
464 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
467 clock-frequency = <24000000>;
468 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
469 clock-names = "baudclk", "apb_pclk";
471 dma-names = "tx", "rx";
472 pinctrl-names = "default";
473 pinctrl-0 = <&uart2m1_xfer>;
474 reg-shift = <2>;
475 reg-io-width = <4>;
480 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
483 clock-frequency = <24000000>;
484 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
485 clock-names = "baudclk", "apb_pclk";
487 dma-names = "tx", "rx";
488 pinctrl-names = "default";
489 pinctrl-0 = <&uart3m0_xfer>;
490 reg-shift = <2>;
491 reg-io-width = <4>;
496 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
499 clock-frequency = <24000000>;
500 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
501 clock-names = "baudclk", "apb_pclk";
503 dma-names = "tx", "rx";
504 pinctrl-names = "default";
505 pinctrl-0 = <&uart4m0_xfer>;
506 reg-shift = <2>;
507 reg-io-width = <4>;
512 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
515 clock-frequency = <24000000>;
516 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
517 clock-names = "baudclk", "apb_pclk";
519 dma-names = "tx", "rx";
520 pinctrl-names = "default";
521 pinctrl-0 = <&uart5m0_xfer>;
522 reg-shift = <2>;
523 reg-io-width = <4>;
528 compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
531 #io-channel-cells = <1>;
532 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
533 clock-names = "saradc", "apb_pclk";
534 resets = <&cru SRST_SARADC_P>;
535 reset-names = "saradc-apb";
540 compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
543 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
544 clock-names = "pclk", "timer";
548 compatible = "rockchip,rv1126-wdt", "snps,dw-wdt";
551 clocks = <&cru PCLK_WDT>;
556 compatible = "rockchip,rv1126-i2s-tdm";
559 clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>;
560 clock-names = "mclk_tx", "mclk_rx", "hclk";
562 dma-names = "tx", "rx";
563 pinctrl-names = "default";
564 pinctrl-0 = <&i2s0m0_sclk_tx>,
574 resets = <&cru SRST_I2S0_TX_M>, <&cru SRST_I2S0_RX_M>;
575 reset-names = "tx-m", "rx-m";
577 #sound-dai-cells = <0>;
582 compatible = "rockchip,rv1126-vop";
585 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
586 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
587 reset-names = "axi", "ahb", "dclk";
588 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
590 power-domains = <&power RV1126_PD_VO>;
594 #address-cells = <1>;
595 #size-cells = <0>;
611 clock-names = "aclk", "iface";
612 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
613 #iommu-cells = <0>;
614 power-domains = <&power RV1126_PD_VO>;
619 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
623 interrupt-names = "macirq", "eth_wake_irq";
625 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
626 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
627 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
628 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
629 clock-names = "stmmaceth", "mac_clk_rx",
633 resets = <&cru SRST_GMAC_A>;
634 reset-names = "stmmaceth";
636 snps,mixed-burst;
639 snps,axi-config = <&stmmac_axi_setup>;
640 snps,mtl-rx-config = <&mtl_rx_setup>;
641 snps,mtl-tx-config = <&mtl_tx_setup>;
645 compatible = "snps,dwmac-mdio";
646 #address-cells = <0x1>;
647 #size-cells = <0x0>;
650 stmmac_axi_setup: stmmac-axi-config {
656 mtl_rx_setup: rx-queues-config {
657 snps,rx-queues-to-use = <1>;
661 mtl_tx_setup: tx-queues-config {
662 snps,tx-queues-to-use = <1>;
668 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
671 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
672 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
673 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
674 fifo-depth = <0x100>;
675 max-frequency = <200000000>;
676 power-domains = <&power RV1126_PD_NVM>;
681 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
684 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
685 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
686 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
687 fifo-depth = <0x100>;
688 max-frequency = <200000000>;
693 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
696 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
697 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
698 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
699 fifo-depth = <0x100>;
700 max-frequency = <200000000>;
701 power-domains = <&power RV1126_PD_SDIO>;
709 assigned-clocks = <&cru SCLK_SFC>;
710 assigned-clock-rates = <80000000>;
711 clock-names = "clk_sfc", "hclk_sfc";
712 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
713 power-domains = <&power RV1126_PD_NVM>;
718 compatible = "rockchip,rv1126-pinctrl";
721 #address-cells = <1>;
722 #size-cells = <1>;
726 compatible = "rockchip,gpio-bank";
730 gpio-controller;
731 #gpio-cells = <2>;
732 interrupt-controller;
733 #interrupt-cells = <2>;
737 compatible = "rockchip,gpio-bank";
740 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
741 gpio-controller;
742 #gpio-cells = <2>;
743 interrupt-controller;
744 #interrupt-cells = <2>;
748 compatible = "rockchip,gpio-bank";
751 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
752 gpio-controller;
753 #gpio-cells = <2>;
754 interrupt-controller;
755 #interrupt-cells = <2>;
759 compatible = "rockchip,gpio-bank";
762 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
763 gpio-controller;
764 #gpio-cells = <2>;
765 interrupt-controller;
766 #interrupt-cells = <2>;
770 compatible = "rockchip,gpio-bank";
773 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
774 gpio-controller;
775 #gpio-cells = <2>;
776 interrupt-controller;
777 #interrupt-cells = <2>;
782 #include "rv1126-pinctrl.dtsi"