Lines Matching +full:0 +full:xff440000
36 #size-cells = <0>;
41 reg = <0xf00>;
49 reg = <0xf01>;
57 reg = <0xf02>;
65 reg = <0xf03>;
103 #clock-cells = <0>;
108 reg = <0xfe000000 0x20000>;
113 reg = <0xfe020000 0x1000>;
123 reg = <0xfe860000 0x20>;
128 reg = <0xfe860080 0x20>;
133 reg = <0xfe860200 0x20>;
138 reg = <0xfe86c000 0x20>;
143 reg = <0xfe8a0000 0x20>;
148 reg = <0xfe8a0080 0x20>;
153 reg = <0xfe8a0100 0x20>;
158 reg = <0xfe8a0180 0x20>;
165 #address-cells = <0>;
167 reg = <0xfeff1000 0x1000>,
168 <0xfeff2000 0x2000>,
169 <0xfeff4000 0x2000>,
170 <0xfeff6000 0x2000>;
176 reg = <0xff3e0000 0x1000>;
182 #size-cells = <0>;
196 #power-domain-cells = <0>;
204 #power-domain-cells = <0>;
223 #power-domain-cells = <0>;
230 reg = <0xff3f0000 0x1000>;
236 pinctrl-0 = <&i2c0_xfer>;
238 #size-cells = <0>;
244 reg = <0xff400000 0x1000>;
250 pinctrl-0 = <&i2c2_xfer>;
252 #size-cells = <0>;
258 reg = <0xff410000 0x100>;
266 pinctrl-0 = <&uart1m0_xfer>;
274 reg = <0xff430000 0x10>;
278 pinctrl-0 = <&pwm0m0_pins>;
285 reg = <0xff430010 0x10>;
289 pinctrl-0 = <&pwm1m0_pins>;
296 reg = <0xff430020 0x10>;
300 pinctrl-0 = <&pwm2m0_pins>;
307 reg = <0xff430030 0x10>;
311 pinctrl-0 = <&pwm3m0_pins>;
318 reg = <0xff440000 0x10>;
322 pinctrl-0 = <&pwm4m0_pins>;
329 reg = <0xff440010 0x10>;
333 pinctrl-0 = <&pwm5m0_pins>;
340 reg = <0xff440020 0x10>;
344 pinctrl-0 = <&pwm6m0_pins>;
351 reg = <0xff440030 0x10>;
355 pinctrl-0 = <&pwm7m0_pins>;
362 reg = <0xff480000 0x1000>;
370 reg = <0xff490000 0x1000>;
380 reg = <0xff4e0000 0x4000>;
391 reg = <0xff520000 0x1000>;
396 pinctrl-0 = <&i2c3m0_xfer>;
399 #size-cells = <0>;
405 reg = <0xff550000 0x10>;
408 pinctrl-0 = <&pwm8m0_pins>;
416 reg = <0xff550010 0x10>;
419 pinctrl-0 = <&pwm9m0_pins>;
427 reg = <0xff550020 0x10>;
430 pinctrl-0 = <&pwm10m0_pins>;
438 reg = <0xff550030 0x10>;
441 pinctrl-0 = <&pwm11m0_pins>;
449 reg = <0xff560000 0x100>;
457 pinctrl-0 = <&uart0_xfer>;
465 reg = <0xff570000 0x100>;
473 pinctrl-0 = <&uart2m1_xfer>;
481 reg = <0xff580000 0x100>;
489 pinctrl-0 = <&uart3m0_xfer>;
497 reg = <0xff590000 0x100>;
505 pinctrl-0 = <&uart4m0_xfer>;
513 reg = <0xff5a0000 0x100>;
521 pinctrl-0 = <&uart5m0_xfer>;
529 reg = <0xff5e0000 0x100>;
541 reg = <0xff660000 0x20>;
549 reg = <0xff680000 0x100>;
557 reg = <0xff800000 0x1000>;
564 pinctrl-0 = <&i2s0m0_sclk_tx>,
577 #sound-dai-cells = <0>;
583 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
595 #size-cells = <0>;
597 vop_out_rgb: endpoint@0 {
598 reg = <0>;
609 reg = <0xffb00f00 0x100>;
613 #iommu-cells = <0>;
620 reg = <0xffc40000 0x4000>;
646 #address-cells = <0x1>;
647 #size-cells = <0x0>;
653 snps,blen = <0 0 0 0 16 8 4>;
669 reg = <0xffc50000 0x4000>;
674 fifo-depth = <0x100>;
682 reg = <0xffc60000 0x4000>;
687 fifo-depth = <0x100>;
694 reg = <0xffc70000 0x4000>;
699 fifo-depth = <0x100>;
707 reg = <0xffc90000 0x4000>;
727 reg = <0xff460000 0x100>;
738 reg = <0xff620000 0x100>;
749 reg = <0xff630000 0x100>;
760 reg = <0xff640000 0x100>;
771 reg = <0xff650000 0x100>;