Lines Matching +full:rk3288 +full:- +full:pmu +full:- +full:sram
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a7";
35 clock-latency = <40000>;
37 #cooling-cells = <2>; /* min followed by max */
38 dynamic-power-coefficient = <75>;
39 operating-points-v2 = <&cpu_opp_table>;
43 cpu_opp_table: opp-table-0 {
44 compatible = "operating-points-v2";
46 opp-408000000 {
47 opp-hz = /bits/ 64 <408000000>;
48 opp-microvolt = <975000>;
49 clock-latency-ns = <40000>;
51 opp-600000000 {
52 opp-hz = /bits/ 64 <600000000>;
53 opp-microvolt = <975000>;
54 clock-latency-ns = <40000>;
56 opp-816000000 {
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1025000>;
59 clock-latency-ns = <40000>;
61 opp-1008000000 {
62 opp-hz = /bits/ 64 <1008000000>;
63 opp-microvolt = <1150000>;
64 clock-latency-ns = <40000>;
68 arm-pmu {
69 compatible = "arm,cortex-a7-pmu";
74 compatible = "arm,armv7-timer";
77 arm,cpu-registers-not-fw-configured;
78 clock-frequency = <24000000>;
82 compatible = "fixed-clock";
83 clock-frequency = <24000000>;
84 clock-output-names = "xin24m";
85 #clock-cells = <0>;
88 bus_intmem: sram@10080000 {
89 compatible = "mmio-sram";
91 #address-cells = <1>;
92 #size-cells = <1>;
97 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
100 reg-shift = <2>;
101 reg-io-width = <4>;
102 clock-frequency = <24000000>;
104 clock-names = "baudclk", "apb_pclk";
106 pinctrl-names = "default";
107 pinctrl-0 = <&uart2m0_xfer>;
112 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
115 reg-shift = <2>;
116 reg-io-width = <4>;
117 clock-frequency = <24000000>;
119 clock-names = "baudclk", "apb_pclk";
121 pinctrl-names = "default";
122 pinctrl-0 = <&uart1_xfer>;
127 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
130 reg-shift = <2>;
131 reg-io-width = <4>;
132 clock-frequency = <24000000>;
134 clock-names = "baudclk", "apb_pclk";
136 pinctrl-names = "default";
137 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
142 compatible = "rockchip,rv1108-i2c";
145 #address-cells = <1>;
146 #size-cells = <0>;
148 clock-names = "i2c", "pclk";
149 pinctrl-names = "default";
150 pinctrl-0 = <&i2c1_xfer>;
156 compatible = "rockchip,rv1108-i2c";
159 #address-cells = <1>;
160 #size-cells = <0>;
162 clock-names = "i2c", "pclk";
163 pinctrl-names = "default";
164 pinctrl-0 = <&i2c2m1_xfer>;
170 compatible = "rockchip,rv1108-i2c";
173 #address-cells = <1>;
174 #size-cells = <0>;
176 clock-names = "i2c", "pclk";
177 pinctrl-names = "default";
178 pinctrl-0 = <&i2c3_xfer>;
184 compatible = "rockchip,rv1108-spi";
188 clock-names = "spiclk", "apb_pclk";
190 dma-names = "tx", "rx";
191 #address-cells = <1>;
192 #size-cells = <0>;
197 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
200 clock-names = "pwm", "pclk";
201 pinctrl-names = "default";
202 pinctrl-0 = <&pwm4_pin>;
203 #pwm-cells = <3>;
208 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
211 clock-names = "pwm", "pclk";
212 pinctrl-names = "default";
213 pinctrl-0 = <&pwm5_pin>;
214 #pwm-cells = <3>;
219 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
222 clock-names = "pwm", "pclk";
223 pinctrl-names = "default";
224 pinctrl-0 = <&pwm6_pin>;
225 #pwm-cells = <3>;
230 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
233 clock-names = "pwm", "pclk";
234 pinctrl-names = "default";
235 pinctrl-0 = <&pwm7_pin>;
236 #pwm-cells = <3>;
240 pdma: dma-controller@102a0000 {
244 #dma-cells = <1>;
245 arm,pl330-broken-no-flushp;
246 arm,pl330-periph-burst;
248 clock-names = "apb_pclk";
252 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
254 #address-cells = <1>;
255 #size-cells = <1>;
257 io_domains: io-domains {
258 compatible = "rockchip,rv1108-io-voltage-domain";
263 compatible = "rockchip,rv1108-usb2phy";
266 clock-names = "phyclk";
267 #clock-cells = <0>;
268 clock-output-names = "usbphy";
272 u2phy_otg: otg-port {
274 interrupt-names = "otg-mux";
275 #phy-cells = <0>;
279 u2phy_host: host-port {
281 interrupt-names = "linestate";
282 #phy-cells = <0>;
289 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
293 clock-names = "pclk", "timer";
297 compatible = "rockchip,rv1108-wdt", "snps,dw-wdt";
304 thermal-zones {
305 soc_thermal: soc-thermal {
306 polling-delay-passive = <20>;
307 polling-delay = <1000>;
308 sustainable-power = <50>;
309 thermal-sensors = <&tsadc 0>;
312 threshold: trip-point0 {
317 target: trip-point1 {
322 soc_crit: soc-crit {
329 cooling-maps {
332 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
340 compatible = "rockchip,rv1108-tsadc";
343 assigned-clocks = <&cru SCLK_TSADC>;
344 assigned-clock-rates = <750000>;
346 clock-names = "tsadc", "apb_pclk";
347 pinctrl-names = "init", "default", "sleep";
348 pinctrl-0 = <&otp_pin>;
349 pinctrl-1 = <&otp_out>;
350 pinctrl-2 = <&otp_pin>;
352 reset-names = "tsadc-apb";
353 rockchip,hw-tshut-temp = <120000>;
354 #thermal-sensor-cells = <1>;
359 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
362 #io-channel-cells = <1>;
364 clock-names = "saradc", "apb_pclk";
369 compatible = "rockchip,rv1108-i2c";
372 #address-cells = <1>;
373 #size-cells = <0>;
375 clock-names = "i2c", "pclk";
376 pinctrl-names = "default";
377 pinctrl-0 = <&i2c0_xfer>;
383 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
386 clock-names = "pwm", "pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&pwm0_pin>;
389 #pwm-cells = <3>;
394 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
397 clock-names = "pwm", "pclk";
398 pinctrl-names = "default";
399 pinctrl-0 = <&pwm1_pin>;
400 #pwm-cells = <3>;
405 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
408 clock-names = "pwm", "pclk";
409 pinctrl-names = "default";
410 pinctrl-0 = <&pwm2_pin>;
411 #pwm-cells = <3>;
416 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
419 clock-names = "pwm", "pclk";
420 pinctrl-names = "default";
421 pinctrl-0 = <&pwm3_pin>;
422 #pwm-cells = <3>;
427 compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd";
430 pmu_io_domains: io-domains {
431 compatible = "rockchip,rv1108-pmu-io-voltage-domain";
437 compatible = "rockchip,rv1108-usbgrf", "syscon";
441 cru: clock-controller@20200000 {
442 compatible = "rockchip,rv1108-cru";
445 clock-names = "xin24m";
447 #clock-cells = <1>;
448 #reset-cells = <1>;
451 nfc: nand-controller@30100000 {
452 compatible = "rockchip,rv1108-nfc";
456 clock-names = "ahb", "nfc";
457 assigned-clocks = <&cru SCLK_NANDC>;
458 assigned-clock-rates = <150000000>;
463 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
468 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
469 fifo-depth = <0x100>;
470 max-frequency = <150000000>;
475 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
480 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
481 fifo-depth = <0x100>;
482 max-frequency = <150000000>;
487 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
492 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
493 fifo-depth = <0x100>;
494 max-frequency = <100000000>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
501 compatible = "generic-ehci";
506 phy-names = "usb";
511 compatible = "generic-ohci";
516 phy-names = "usb";
521 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
526 clock-names = "otg";
528 g-np-tx-fifo-size = <16>;
529 g-rx-fifo-size = <280>;
530 g-tx-fifo-size = <256 128 128 64 32 16>;
532 phy-names = "usb2-phy";
541 clock-names = "clk_sfc", "hclk_sfc";
542 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
543 pinctrl-names = "default";
548 compatible = "rockchip,rv1108-gmac";
552 interrupt-names = "macirq", "eth_wake_irq";
557 clock-names = "stmmaceth",
562 phy-mode = "rmii";
563 pinctrl-names = "default";
564 pinctrl-0 = <&rmii_pins>;
569 gic: interrupt-controller@32010000 {
570 compatible = "arm,gic-400";
571 interrupt-controller;
572 #interrupt-cells = <3>;
573 #address-cells = <0>;
583 compatible = "rockchip,rv1108-pinctrl";
585 rockchip,pmu = <&pmugrf>;
586 #address-cells = <1>;
587 #size-cells = <1>;
591 compatible = "rockchip,gpio-bank";
596 gpio-controller;
597 #gpio-cells = <2>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
604 compatible = "rockchip,gpio-bank";
609 gpio-controller;
610 #gpio-cells = <2>;
612 interrupt-controller;
613 #interrupt-cells = <2>;
617 compatible = "rockchip,gpio-bank";
622 gpio-controller;
623 #gpio-cells = <2>;
625 interrupt-controller;
626 #interrupt-cells = <2>;
630 compatible = "rockchip,gpio-bank";
635 gpio-controller;
636 #gpio-cells = <2>;
638 interrupt-controller;
639 #interrupt-cells = <2>;
642 pcfg_pull_up: pcfg-pull-up {
643 bias-pull-up;
646 pcfg_pull_down: pcfg-pull-down {
647 bias-pull-down;
650 pcfg_pull_none: pcfg-pull-none {
651 bias-disable;
654 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
655 drive-strength = <8>;
658 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
659 drive-strength = <12>;
662 pcfg_pull_none_smt: pcfg-pull-none-smt {
663 bias-disable;
664 input-schmitt-enable;
667 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
668 bias-pull-up;
669 drive-strength = <8>;
672 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
673 drive-strength = <4>;
676 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
677 bias-pull-up;
678 drive-strength = <4>;
681 pcfg_output_high: pcfg-output-high {
682 output-high;
685 pcfg_output_low: pcfg-output-low {
686 output-low;
689 pcfg_input_high: pcfg-input-high {
690 bias-pull-up;
691 input-enable;
695 emmc_bus8: emmc-bus8 {
706 emmc_clk: emmc-clk {
710 emmc_cmd: emmc-cmd {
716 sfc_bus4: sfc-bus4 {
724 sfc_bus2: sfc-bus2 {
730 sfc_cs0: sfc-cs0 {
735 sfc_clk: sfc-clk {
742 rmii_pins: rmii-pins {
757 i2c0_xfer: i2c0-xfer {
764 i2c1_xfer: i2c1-xfer {
771 i2c2m1_xfer: i2c2m1-xfer {
776 i2c2m1_pins: i2c2m1-pins {
783 i2c2m05v_xfer: i2c2m05v-xfer {
788 i2c2m05v_pins: i2c2m05v-pins {
795 i2c3_xfer: i2c3-xfer {
802 pwm0_pin: pwm0-pin {
808 pwm1_pin: pwm1-pin {
814 pwm2_pin: pwm2-pin {
820 pwm3_pin: pwm3-pin {
826 pwm4_pin: pwm4-pin {
832 pwm5_pin: pwm5-pin {
838 pwm6_pin: pwm6-pin {
844 pwm7_pin: pwm7-pin {
850 sdmmc_clk: sdmmc-clk {
854 sdmmc_cmd: sdmmc-cmd {
858 sdmmc_cd: sdmmc-cd {
862 sdmmc_bus1: sdmmc-bus1 {
866 sdmmc_bus4: sdmmc-bus4 {
875 spim0_clk: spim0-clk {
879 spim0_cs0: spim0-cs0 {
883 spim0_tx: spim0-tx {
887 spim0_rx: spim0-rx {
893 spim1_clk: spim1-clk {
897 spim1_cs0: spim1-cs0 {
901 spim1_rx: spim1-rx {
905 spim1_tx: spim1-tx {
911 otp_out: otp-out {
915 otp_pin: otp-pin {
921 uart0_xfer: uart0-xfer {
926 uart0_cts: uart0-cts {
930 uart0_rts: uart0-rts {
934 uart0_rts_pin: uart0-rts-pin {
940 uart1_xfer: uart1-xfer {
945 uart1_cts: uart1-cts {
949 uart1_rts: uart1-rts {
955 uart2m0_xfer: uart2m0-xfer {
962 uart2m1_xfer: uart2m1-xfer {
969 uart2_5v_cts: uart2_5v-cts {
973 uart2_5v_rts: uart2_5v-rts {