Lines Matching +full:rk2928 +full:- +full:pwm
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
37 compatible = "fixed-clock";
38 clock-frequency = <24000000>;
39 #clock-cells = <0>;
40 clock-output-names = "xin24m";
44 compatible = "arm,mali-400";
47 clock-names = "bus", "core";
48 assigned-clocks = <&cru ACLK_GPU>;
49 assigned-clock-rates = <100000000>;
54 vpu: video-codec@10104000 {
55 compatible = "rockchip,rk3066-vpu";
59 interrupt-names = "vepu", "vdpu";
62 clock-names = "aclk_vdpu", "hclk_vdpu",
66 L2: cache-controller@10138000 {
67 compatible = "arm,pl310-cache";
69 cache-unified;
70 cache-level = <2>;
74 compatible = "arm,cortex-a9-scu";
78 global_timer: global-timer@1013c200 {
79 compatible = "arm,cortex-a9-global-timer";
92 local_timer: local-timer@1013c600 {
93 compatible = "arm,cortex-a9-twd-timer";
99 gic: interrupt-controller@1013d000 {
100 compatible = "arm,cortex-a9-gic";
101 interrupt-controller;
102 #interrupt-cells = <3>;
108 compatible = "snps,dw-apb-uart";
111 reg-shift = <2>;
112 reg-io-width = <1>;
113 clock-names = "baudclk", "apb_pclk";
119 compatible = "snps,dw-apb-uart";
122 reg-shift = <2>;
123 reg-io-width = <1>;
124 clock-names = "baudclk", "apb_pclk";
130 compatible = "rockchip,rk3066-qos", "syscon";
135 compatible = "rockchip,rk3066-qos", "syscon";
140 compatible = "rockchip,rk3066-qos", "syscon";
145 compatible = "rockchip,rk3066-qos", "syscon";
150 compatible = "rockchip,rk3066-qos", "syscon";
155 compatible = "rockchip,rk3066-qos", "syscon";
160 compatible = "rockchip,rk3066-qos", "syscon";
165 compatible = "rockchip,rk3066-qos", "syscon";
170 compatible = "rockchip,rk3066-usb", "snps,dwc2";
174 clock-names = "otg";
176 g-np-tx-fifo-size = <16>;
177 g-rx-fifo-size = <275>;
178 g-tx-fifo-size = <256 128 128 64 64 32>;
180 phy-names = "usb2-phy";
189 clock-names = "otg";
192 phy-names = "usb2-phy";
197 compatible = "rockchip,rk3066-emac";
201 clock-names = "hclk", "macref";
202 max-speed = <100>;
203 phy-mode = "rmii";
209 compatible = "rockchip,rk2928-dw-mshc";
213 clock-names = "biu", "ciu";
215 dma-names = "rx-tx";
216 fifo-depth = <256>;
218 reset-names = "reset";
223 compatible = "rockchip,rk2928-dw-mshc";
227 clock-names = "biu", "ciu";
229 dma-names = "rx-tx";
230 fifo-depth = <256>;
232 reset-names = "reset";
237 compatible = "rockchip,rk2928-dw-mshc";
241 clock-names = "biu", "ciu";
243 dma-names = "rx-tx";
244 fifo-depth = <256>;
246 reset-names = "reset";
250 nfc: nand-controller@10500000 {
251 compatible = "rockchip,rk2928-nfc";
255 clock-names = "ahb";
260 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
263 reboot-mode {
264 compatible = "syscon-reboot-mode";
266 mode-normal = <BOOT_NORMAL>;
267 mode-recovery = <BOOT_RECOVERY>;
268 mode-bootloader = <BOOT_FASTBOOT>;
269 mode-loader = <BOOT_BL_DOWNLOAD>;
274 compatible = "syscon", "simple-mfd";
278 dmac1_s: dma-controller@20018000 {
283 #dma-cells = <1>;
284 arm,pl330-broken-no-flushp;
285 arm,pl330-periph-burst;
287 clock-names = "apb_pclk";
290 dmac1_ns: dma-controller@2001c000 {
295 #dma-cells = <1>;
296 arm,pl330-broken-no-flushp;
297 arm,pl330-periph-burst;
299 clock-names = "apb_pclk";
304 compatible = "rockchip,rk3066-i2c";
307 #address-cells = <1>;
308 #size-cells = <0>;
312 clock-names = "i2c";
319 compatible = "rockchip,rk3066-i2c";
322 #address-cells = <1>;
323 #size-cells = <0>;
328 clock-names = "i2c";
333 pwm0: pwm@20030000 {
334 compatible = "rockchip,rk2928-pwm";
336 #pwm-cells = <2>;
341 pwm1: pwm@20030010 {
342 compatible = "rockchip,rk2928-pwm";
344 #pwm-cells = <2>;
350 compatible = "snps,dw-wdt";
357 pwm2: pwm@20050020 {
358 compatible = "rockchip,rk2928-pwm";
360 #pwm-cells = <2>;
365 pwm3: pwm@20050030 {
366 compatible = "rockchip,rk2928-pwm";
368 #pwm-cells = <2>;
374 compatible = "rockchip,rk3066-i2c";
377 #address-cells = <1>;
378 #size-cells = <0>;
383 clock-names = "i2c";
389 compatible = "rockchip,rk3066-i2c";
392 #address-cells = <1>;
393 #size-cells = <0>;
398 clock-names = "i2c";
404 compatible = "rockchip,rk3066-i2c";
407 #address-cells = <1>;
408 #size-cells = <0>;
413 clock-names = "i2c";
419 compatible = "snps,dw-apb-uart";
422 reg-shift = <2>;
423 reg-io-width = <1>;
424 clock-names = "baudclk", "apb_pclk";
430 compatible = "snps,dw-apb-uart";
433 reg-shift = <2>;
434 reg-io-width = <1>;
435 clock-names = "baudclk", "apb_pclk";
444 #io-channel-cells = <1>;
446 clock-names = "saradc", "apb_pclk";
448 reset-names = "saradc-apb";
453 compatible = "rockchip,rk3066-spi";
455 clock-names = "spiclk", "apb_pclk";
458 #address-cells = <1>;
459 #size-cells = <0>;
461 dma-names = "tx", "rx";
466 compatible = "rockchip,rk3066-spi";
468 clock-names = "spiclk", "apb_pclk";
471 #address-cells = <1>;
472 #size-cells = <0>;
474 dma-names = "tx", "rx";
478 dmac2: dma-controller@20078000 {
483 #dma-cells = <1>;
484 arm,pl330-broken-no-flushp;
485 arm,pl330-periph-burst;
487 clock-names = "apb_pclk";