Lines Matching +full:rk3288 +full:- +full:dp +full:- +full:phy
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 compatible = "rockchip,rk3288";
18 interrupt-parent = <&gic>;
51 arm-pmu {
52 compatible = "arm,cortex-a12-pmu";
57 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
61 #address-cells = <1>;
62 #size-cells = <0>;
63 enable-method = "rockchip,rk3066-smp";
68 compatible = "arm,cortex-a12";
71 operating-points-v2 = <&cpu_opp_table>;
72 #cooling-cells = <2>; /* min followed by max */
74 dynamic-power-coefficient = <370>;
78 compatible = "arm,cortex-a12";
81 operating-points-v2 = <&cpu_opp_table>;
82 #cooling-cells = <2>; /* min followed by max */
84 dynamic-power-coefficient = <370>;
88 compatible = "arm,cortex-a12";
91 operating-points-v2 = <&cpu_opp_table>;
92 #cooling-cells = <2>; /* min followed by max */
94 dynamic-power-coefficient = <370>;
98 compatible = "arm,cortex-a12";
101 operating-points-v2 = <&cpu_opp_table>;
102 #cooling-cells = <2>; /* min followed by max */
104 dynamic-power-coefficient = <370>;
108 cpu_opp_table: opp-table-0 {
109 compatible = "operating-points-v2";
110 opp-shared;
112 opp-126000000 {
113 opp-hz = /bits/ 64 <126000000>;
114 opp-microvolt = <900000>;
115 clock-latency-ns = <40000>;
117 opp-216000000 {
118 opp-hz = /bits/ 64 <216000000>;
119 opp-microvolt = <900000>;
121 opp-312000000 {
122 opp-hz = /bits/ 64 <312000000>;
123 opp-microvolt = <900000>;
125 opp-408000000 {
126 opp-hz = /bits/ 64 <408000000>;
127 opp-microvolt = <900000>;
129 opp-600000000 {
130 opp-hz = /bits/ 64 <600000000>;
131 opp-microvolt = <900000>;
133 opp-696000000 {
134 opp-hz = /bits/ 64 <696000000>;
135 opp-microvolt = <950000>;
137 opp-816000000 {
138 opp-hz = /bits/ 64 <816000000>;
139 opp-microvolt = <1000000>;
141 opp-1008000000 {
142 opp-hz = /bits/ 64 <1008000000>;
143 opp-microvolt = <1050000>;
145 opp-1200000000 {
146 opp-hz = /bits/ 64 <1200000000>;
147 opp-microvolt = <1100000>;
149 opp-1416000000 {
150 opp-hz = /bits/ 64 <1416000000>;
151 opp-microvolt = <1200000>;
153 opp-1512000000 {
154 opp-hz = /bits/ 64 <1512000000>;
155 opp-microvolt = <1300000>;
157 opp-1608000000 {
158 opp-hz = /bits/ 64 <1608000000>;
159 opp-microvolt = <1350000>;
163 reserved-memory {
164 #address-cells = <2>;
165 #size-cells = <2>;
169 * The rk3288 cannot use the memory area above 0xfe000000
178 dma-unusable@fe000000 {
184 compatible = "fixed-clock";
185 clock-frequency = <24000000>;
186 clock-output-names = "xin24m";
187 #clock-cells = <0>;
191 compatible = "arm,armv7-timer";
192 arm,cpu-registers-not-fw-configured;
197 clock-frequency = <24000000>;
198 arm,no-tick-in-suspend;
202 compatible = "rockchip,rk3288-timer";
206 clock-names = "pclk", "timer";
209 display-subsystem {
210 compatible = "rockchip,display-subsystem";
215 compatible = "rockchip,rk3288-dw-mshc";
216 max-frequency = <150000000>;
219 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
220 fifo-depth = <0x100>;
224 reset-names = "reset";
229 compatible = "rockchip,rk3288-dw-mshc";
230 max-frequency = <150000000>;
233 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
234 fifo-depth = <0x100>;
238 reset-names = "reset";
243 compatible = "rockchip,rk3288-dw-mshc";
244 max-frequency = <150000000>;
247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
248 fifo-depth = <0x100>;
252 reset-names = "reset";
257 compatible = "rockchip,rk3288-dw-mshc";
258 max-frequency = <150000000>;
261 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
262 fifo-depth = <0x100>;
266 reset-names = "reset";
274 #io-channel-cells = <1>;
276 clock-names = "saradc", "apb_pclk";
278 reset-names = "saradc-apb";
283 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
285 clock-names = "spiclk", "apb_pclk";
287 dma-names = "tx", "rx";
289 pinctrl-names = "default";
290 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
292 #address-cells = <1>;
293 #size-cells = <0>;
298 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
300 clock-names = "spiclk", "apb_pclk";
302 dma-names = "tx", "rx";
304 pinctrl-names = "default";
305 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
307 #address-cells = <1>;
308 #size-cells = <0>;
313 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
315 clock-names = "spiclk", "apb_pclk";
317 dma-names = "tx", "rx";
319 pinctrl-names = "default";
320 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
322 #address-cells = <1>;
323 #size-cells = <0>;
328 compatible = "rockchip,rk3288-i2c";
331 #address-cells = <1>;
332 #size-cells = <0>;
333 clock-names = "i2c";
335 pinctrl-names = "default";
336 pinctrl-0 = <&i2c1_xfer>;
341 compatible = "rockchip,rk3288-i2c";
344 #address-cells = <1>;
345 #size-cells = <0>;
346 clock-names = "i2c";
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c3_xfer>;
354 compatible = "rockchip,rk3288-i2c";
357 #address-cells = <1>;
358 #size-cells = <0>;
359 clock-names = "i2c";
361 pinctrl-names = "default";
362 pinctrl-0 = <&i2c4_xfer>;
367 compatible = "rockchip,rk3288-i2c";
370 #address-cells = <1>;
371 #size-cells = <0>;
372 clock-names = "i2c";
374 pinctrl-names = "default";
375 pinctrl-0 = <&i2c5_xfer>;
380 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
383 reg-shift = <2>;
384 reg-io-width = <4>;
386 clock-names = "baudclk", "apb_pclk";
388 dma-names = "tx", "rx";
389 pinctrl-names = "default";
390 pinctrl-0 = <&uart0_xfer>;
395 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
398 reg-shift = <2>;
399 reg-io-width = <4>;
401 clock-names = "baudclk", "apb_pclk";
403 dma-names = "tx", "rx";
404 pinctrl-names = "default";
405 pinctrl-0 = <&uart1_xfer>;
410 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
413 reg-shift = <2>;
414 reg-io-width = <4>;
416 clock-names = "baudclk", "apb_pclk";
417 pinctrl-names = "default";
418 pinctrl-0 = <&uart2_xfer>;
423 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
426 reg-shift = <2>;
427 reg-io-width = <4>;
429 clock-names = "baudclk", "apb_pclk";
431 dma-names = "tx", "rx";
432 pinctrl-names = "default";
433 pinctrl-0 = <&uart3_xfer>;
438 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
441 reg-shift = <2>;
442 reg-io-width = <4>;
444 clock-names = "baudclk", "apb_pclk";
446 dma-names = "tx", "rx";
447 pinctrl-names = "default";
448 pinctrl-0 = <&uart4_xfer>;
452 dmac_peri: dma-controller@ff250000 {
457 #dma-cells = <1>;
458 arm,pl330-broken-no-flushp;
459 arm,pl330-periph-burst;
461 clock-names = "apb_pclk";
464 thermal-zones {
465 reserve_thermal: reserve-thermal {
466 polling-delay-passive = <1000>; /* milliseconds */
467 polling-delay = <5000>; /* milliseconds */
469 thermal-sensors = <&tsadc 0>;
472 cpu_thermal: cpu-thermal {
473 polling-delay-passive = <100>; /* milliseconds */
474 polling-delay = <5000>; /* milliseconds */
476 thermal-sensors = <&tsadc 1>;
496 cooling-maps {
499 cooling-device =
507 cooling-device =
516 gpu_thermal: gpu-thermal {
517 polling-delay-passive = <100>; /* milliseconds */
518 polling-delay = <5000>; /* milliseconds */
520 thermal-sensors = <&tsadc 2>;
535 cooling-maps {
538 cooling-device =
546 compatible = "rockchip,rk3288-tsadc";
550 clock-names = "tsadc", "apb_pclk";
552 reset-names = "tsadc-apb";
553 pinctrl-names = "init", "default", "sleep";
554 pinctrl-0 = <&otp_pin>;
555 pinctrl-1 = <&otp_out>;
556 pinctrl-2 = <&otp_pin>;
557 #thermal-sensor-cells = <1>;
559 rockchip,hw-tshut-temp = <95000>;
564 compatible = "rockchip,rk3288-gmac";
568 interrupt-names = "macirq", "eth_wake_irq";
574 clock-names = "stmmaceth",
579 reset-names = "stmmaceth";
584 compatible = "generic-ehci";
589 phy-names = "usb";
593 /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
595 compatible = "generic-ohci";
600 phy-names = "usb";
605 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
610 clock-names = "otg";
613 phy-names = "usb2-phy";
614 snps,reset-phy-on-wake;
619 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
624 clock-names = "otg";
626 g-np-tx-fifo-size = <16>;
627 g-rx-fifo-size = <275>;
628 g-tx-fifo-size = <256 128 128 64 64 32>;
630 phy-names = "usb2-phy";
635 compatible = "generic-ehci";
642 dmac_bus_ns: dma-controller@ff600000 {
647 #dma-cells = <1>;
648 arm,pl330-broken-no-flushp;
649 arm,pl330-periph-burst;
651 clock-names = "apb_pclk";
656 compatible = "rockchip,rk3288-i2c";
659 #address-cells = <1>;
660 #size-cells = <0>;
661 clock-names = "i2c";
663 pinctrl-names = "default";
664 pinctrl-0 = <&i2c0_xfer>;
669 compatible = "rockchip,rk3288-i2c";
672 #address-cells = <1>;
673 #size-cells = <0>;
674 clock-names = "i2c";
676 pinctrl-names = "default";
677 pinctrl-0 = <&i2c2_xfer>;
682 compatible = "rockchip,rk3288-pwm";
684 #pwm-cells = <3>;
685 pinctrl-names = "default";
686 pinctrl-0 = <&pwm0_pin>;
692 compatible = "rockchip,rk3288-pwm";
694 #pwm-cells = <3>;
695 pinctrl-names = "default";
696 pinctrl-0 = <&pwm1_pin>;
702 compatible = "rockchip,rk3288-pwm";
704 #pwm-cells = <3>;
705 pinctrl-names = "default";
706 pinctrl-0 = <&pwm2_pin>;
712 compatible = "rockchip,rk3288-pwm";
714 #pwm-cells = <3>;
715 pinctrl-names = "default";
716 pinctrl-0 = <&pwm3_pin>;
722 compatible = "mmio-sram";
724 #address-cells = <1>;
725 #size-cells = <1>;
727 smp-sram@0 {
728 compatible = "rockchip,rk3066-smp-sram";
734 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
738 pmu: power-management@ff730000 {
739 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
742 power: power-controller {
743 compatible = "rockchip,rk3288-power-controller";
744 #power-domain-cells = <1>;
745 #address-cells = <1>;
746 #size-cells = <0>;
748 assigned-clocks = <&cru SCLK_EDP_24M>;
749 assigned-clock-parents = <&xin24m>;
774 power-domain@RK3288_PD_VIO {
810 #power-domain-cells = <0>;
817 power-domain@RK3288_PD_HEVC {
824 #power-domain-cells = <0>;
832 power-domain@RK3288_PD_VIDEO {
837 #power-domain-cells = <0>;
844 power-domain@RK3288_PD_GPU {
849 #power-domain-cells = <0>;
853 reboot-mode {
854 compatible = "syscon-reboot-mode";
856 mode-normal = <BOOT_NORMAL>;
857 mode-recovery = <BOOT_RECOVERY>;
858 mode-bootloader = <BOOT_FASTBOOT>;
859 mode-loader = <BOOT_BL_DOWNLOAD>;
864 compatible = "rockchip,rk3288-sgrf", "syscon";
868 cru: clock-controller@ff760000 {
869 compatible = "rockchip,rk3288-cru";
872 clock-names = "xin24m";
874 #clock-cells = <1>;
875 #reset-cells = <1>;
876 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
881 assigned-clock-rates = <594000000>, <400000000>,
889 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
892 edp_phy: edp-phy {
893 compatible = "rockchip,rk3288-dp-phy";
895 clock-names = "24m";
896 #phy-cells = <0>;
900 io_domains: io-domains {
901 compatible = "rockchip,rk3288-io-voltage-domain";
906 compatible = "rockchip,rk3288-usb-phy";
907 #address-cells = <1>;
908 #size-cells = <0>;
911 usbphy0: usb-phy@320 {
912 #phy-cells = <0>;
915 clock-names = "phyclk";
916 #clock-cells = <0>;
918 reset-names = "phy-reset";
921 usbphy1: usb-phy@334 {
922 #phy-cells = <0>;
925 clock-names = "phyclk";
926 #clock-cells = <0>;
928 reset-names = "phy-reset";
931 usbphy2: usb-phy@348 {
932 #phy-cells = <0>;
935 clock-names = "phyclk";
936 #clock-cells = <0>;
938 reset-names = "phy-reset";
944 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
952 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
954 #sound-dai-cells = <0>;
956 clock-names = "mclk", "hclk";
958 dma-names = "tx";
960 pinctrl-names = "default";
961 pinctrl-0 = <&spdif_tx>;
967 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
969 #sound-dai-cells = <0>;
972 clock-names = "i2s_clk", "i2s_hclk";
974 dma-names = "tx", "rx";
975 pinctrl-names = "default";
976 pinctrl-0 = <&i2s0_bus>;
977 rockchip,playback-channels = <8>;
978 rockchip,capture-channels = <2>;
983 compatible = "rockchip,rk3288-crypto";
988 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
990 reset-names = "crypto-rst";
998 clock-names = "aclk", "iface";
999 #iommu-cells = <0>;
1008 clock-names = "aclk", "iface";
1009 #iommu-cells = <0>;
1010 rockchip,disable-mmu-reset;
1015 compatible = "rockchip,rk3288-rga";
1019 clock-names = "aclk", "hclk", "sclk";
1020 power-domains = <&power RK3288_PD_VIO>;
1022 reset-names = "core", "axi", "ahb";
1026 compatible = "rockchip,rk3288-vop";
1030 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1031 power-domains = <&power RK3288_PD_VIO>;
1033 reset-names = "axi", "ahb", "dclk";
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1043 remote-endpoint = <&hdmi_in_vopb>;
1048 remote-endpoint = <&edp_in_vopb>;
1053 remote-endpoint = <&mipi_in_vopb>;
1058 remote-endpoint = <&lvds_in_vopb>;
1068 clock-names = "aclk", "iface";
1069 power-domains = <&power RK3288_PD_VIO>;
1070 #iommu-cells = <0>;
1075 compatible = "rockchip,rk3288-vop";
1079 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1080 power-domains = <&power RK3288_PD_VIO>;
1082 reset-names = "axi", "ahb", "dclk";
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1092 remote-endpoint = <&hdmi_in_vopl>;
1097 remote-endpoint = <&edp_in_vopl>;
1102 remote-endpoint = <&mipi_in_vopl>;
1107 remote-endpoint = <&lvds_in_vopl>;
1117 clock-names = "aclk", "iface";
1118 power-domains = <&power RK3288_PD_VIO>;
1119 #iommu-cells = <0>;
1124 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1128 clock-names = "ref", "pclk";
1129 power-domains = <&power RK3288_PD_VIO>;
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1144 remote-endpoint = <&vopb_out_mipi>;
1149 remote-endpoint = <&vopl_out_mipi>;
1160 compatible = "rockchip,rk3288-lvds";
1163 clock-names = "pclk_lvds";
1164 pinctrl-names = "lcdc";
1165 pinctrl-0 = <&lcdc_ctl>;
1166 power-domains = <&power RK3288_PD_VIO>;
1171 #address-cells = <1>;
1172 #size-cells = <0>;
1176 #address-cells = <1>;
1177 #size-cells = <0>;
1181 remote-endpoint = <&vopb_out_lvds>;
1186 remote-endpoint = <&vopl_out_lvds>;
1196 edp: dp@ff970000 {
1197 compatible = "rockchip,rk3288-dp";
1201 clock-names = "dp", "pclk";
1203 phy-names = "dp";
1204 power-domains = <&power RK3288_PD_VIO>;
1206 reset-names = "dp";
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1221 remote-endpoint = <&vopb_out_edp>;
1226 remote-endpoint = <&vopl_out_edp>;
1237 compatible = "rockchip,rk3288-dw-hdmi";
1239 reg-io-width = <4>;
1242 clock-names = "iahb", "isfr", "cec";
1243 power-domains = <&power RK3288_PD_VIO>;
1245 #sound-dai-cells = <0>;
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1259 remote-endpoint = <&vopb_out_hdmi>;
1264 remote-endpoint = <&vopl_out_hdmi>;
1274 vpu: video-codec@ff9a0000 {
1275 compatible = "rockchip,rk3288-vpu";
1279 interrupt-names = "vepu", "vdpu";
1281 clock-names = "aclk", "hclk";
1283 power-domains = <&power RK3288_PD_VIDEO>;
1291 clock-names = "aclk", "iface";
1292 #iommu-cells = <0>;
1293 power-domains = <&power RK3288_PD_VIDEO>;
1301 clock-names = "aclk", "iface";
1302 #iommu-cells = <0>;
1307 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1312 interrupt-names = "job", "mmu", "gpu";
1314 operating-points-v2 = <&gpu_opp_table>;
1315 #cooling-cells = <2>; /* min followed by max */
1316 power-domains = <&power RK3288_PD_GPU>;
1320 gpu_opp_table: opp-table-1 {
1321 compatible = "operating-points-v2";
1323 opp-100000000 {
1324 opp-hz = /bits/ 64 <100000000>;
1325 opp-microvolt = <950000>;
1327 opp-200000000 {
1328 opp-hz = /bits/ 64 <200000000>;
1329 opp-microvolt = <950000>;
1331 opp-300000000 {
1332 opp-hz = /bits/ 64 <300000000>;
1333 opp-microvolt = <1000000>;
1335 opp-400000000 {
1336 opp-hz = /bits/ 64 <400000000>;
1337 opp-microvolt = <1100000>;
1339 opp-600000000 {
1340 opp-hz = /bits/ 64 <600000000>;
1341 opp-microvolt = <1250000>;
1346 compatible = "rockchip,rk3288-qos", "syscon";
1351 compatible = "rockchip,rk3288-qos", "syscon";
1356 compatible = "rockchip,rk3288-qos", "syscon";
1361 compatible = "rockchip,rk3288-qos", "syscon";
1366 compatible = "rockchip,rk3288-qos", "syscon";
1371 compatible = "rockchip,rk3288-qos", "syscon";
1376 compatible = "rockchip,rk3288-qos", "syscon";
1381 compatible = "rockchip,rk3288-qos", "syscon";
1386 compatible = "rockchip,rk3288-qos", "syscon";
1391 compatible = "rockchip,rk3288-qos", "syscon";
1396 compatible = "rockchip,rk3288-qos", "syscon";
1401 compatible = "rockchip,rk3288-qos", "syscon";
1406 compatible = "rockchip,rk3288-qos", "syscon";
1411 compatible = "rockchip,rk3288-qos", "syscon";
1415 dmac_bus_s: dma-controller@ffb20000 {
1420 #dma-cells = <1>;
1421 arm,pl330-broken-no-flushp;
1422 arm,pl330-periph-burst;
1424 clock-names = "apb_pclk";
1428 compatible = "rockchip,rk3288-efuse";
1430 #address-cells = <1>;
1431 #size-cells = <1>;
1433 clock-names = "pclk_efuse";
1435 cpu_id: cpu-id@7 {
1443 gic: interrupt-controller@ffc01000 {
1444 compatible = "arm,gic-400";
1445 interrupt-controller;
1446 #interrupt-cells = <3>;
1447 #address-cells = <0>;
1457 compatible = "rockchip,rk3288-pinctrl";
1460 #address-cells = <2>;
1461 #size-cells = <2>;
1465 compatible = "rockchip,gpio-bank";
1470 gpio-controller;
1471 #gpio-cells = <2>;
1473 interrupt-controller;
1474 #interrupt-cells = <2>;
1478 compatible = "rockchip,gpio-bank";
1483 gpio-controller;
1484 #gpio-cells = <2>;
1486 interrupt-controller;
1487 #interrupt-cells = <2>;
1491 compatible = "rockchip,gpio-bank";
1496 gpio-controller;
1497 #gpio-cells = <2>;
1499 interrupt-controller;
1500 #interrupt-cells = <2>;
1504 compatible = "rockchip,gpio-bank";
1509 gpio-controller;
1510 #gpio-cells = <2>;
1512 interrupt-controller;
1513 #interrupt-cells = <2>;
1517 compatible = "rockchip,gpio-bank";
1522 gpio-controller;
1523 #gpio-cells = <2>;
1525 interrupt-controller;
1526 #interrupt-cells = <2>;
1530 compatible = "rockchip,gpio-bank";
1535 gpio-controller;
1536 #gpio-cells = <2>;
1538 interrupt-controller;
1539 #interrupt-cells = <2>;
1543 compatible = "rockchip,gpio-bank";
1548 gpio-controller;
1549 #gpio-cells = <2>;
1551 interrupt-controller;
1552 #interrupt-cells = <2>;
1556 compatible = "rockchip,gpio-bank";
1561 gpio-controller;
1562 #gpio-cells = <2>;
1564 interrupt-controller;
1565 #interrupt-cells = <2>;
1569 compatible = "rockchip,gpio-bank";
1574 gpio-controller;
1575 #gpio-cells = <2>;
1577 interrupt-controller;
1578 #interrupt-cells = <2>;
1582 hdmi_cec_c0: hdmi-cec-c0 {
1586 hdmi_cec_c7: hdmi-cec-c7 {
1590 hdmi_ddc: hdmi-ddc {
1595 hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1601 pcfg_output_low: pcfg-output-low {
1602 output-low;
1605 pcfg_pull_up: pcfg-pull-up {
1606 bias-pull-up;
1609 pcfg_pull_down: pcfg-pull-down {
1610 bias-pull-down;
1613 pcfg_pull_none: pcfg-pull-none {
1614 bias-disable;
1617 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1618 bias-disable;
1619 drive-strength = <12>;
1623 global_pwroff: global-pwroff {
1627 ddrio_pwroff: ddrio-pwroff {
1631 ddr0_retention: ddr0-retention {
1635 ddr1_retention: ddr1-retention {
1641 edp_hpd: edp-hpd {
1647 i2c0_xfer: i2c0-xfer {
1654 i2c1_xfer: i2c1-xfer {
1661 i2c2_xfer: i2c2-xfer {
1668 i2c3_xfer: i2c3-xfer {
1675 i2c4_xfer: i2c4-xfer {
1682 i2c5_xfer: i2c5-xfer {
1689 i2s0_bus: i2s0-bus {
1700 lcdc_ctl: lcdc-ctl {
1709 sdmmc_clk: sdmmc-clk {
1713 sdmmc_cmd: sdmmc-cmd {
1717 sdmmc_cd: sdmmc-cd {
1721 sdmmc_bus1: sdmmc-bus1 {
1725 sdmmc_bus4: sdmmc-bus4 {
1734 sdio0_bus1: sdio0-bus1 {
1738 sdio0_bus4: sdio0-bus4 {
1745 sdio0_cmd: sdio0-cmd {
1749 sdio0_clk: sdio0-clk {
1753 sdio0_cd: sdio0-cd {
1757 sdio0_wp: sdio0-wp {
1761 sdio0_pwr: sdio0-pwr {
1765 sdio0_bkpwr: sdio0-bkpwr {
1769 sdio0_int: sdio0-int {
1775 sdio1_bus1: sdio1-bus1 {
1779 sdio1_bus4: sdio1-bus4 {
1786 sdio1_cd: sdio1-cd {
1790 sdio1_wp: sdio1-wp {
1794 sdio1_bkpwr: sdio1-bkpwr {
1798 sdio1_int: sdio1-int {
1802 sdio1_cmd: sdio1-cmd {
1806 sdio1_clk: sdio1-clk {
1810 sdio1_pwr: sdio1-pwr {
1816 emmc_clk: emmc-clk {
1820 emmc_cmd: emmc-cmd {
1824 emmc_pwr: emmc-pwr {
1828 emmc_bus1: emmc-bus1 {
1832 emmc_bus4: emmc-bus4 {
1839 emmc_bus8: emmc-bus8 {
1852 spi0_clk: spi0-clk {
1855 spi0_cs0: spi0-cs0 {
1858 spi0_tx: spi0-tx {
1861 spi0_rx: spi0-rx {
1864 spi0_cs1: spi0-cs1 {
1869 spi1_clk: spi1-clk {
1872 spi1_cs0: spi1-cs0 {
1875 spi1_rx: spi1-rx {
1878 spi1_tx: spi1-tx {
1884 spi2_cs1: spi2-cs1 {
1887 spi2_clk: spi2-clk {
1890 spi2_cs0: spi2-cs0 {
1893 spi2_rx: spi2-rx {
1896 spi2_tx: spi2-tx {
1902 uart0_xfer: uart0-xfer {
1907 uart0_cts: uart0-cts {
1911 uart0_rts: uart0-rts {
1917 uart1_xfer: uart1-xfer {
1922 uart1_cts: uart1-cts {
1926 uart1_rts: uart1-rts {
1932 uart2_xfer: uart2-xfer {
1940 uart3_xfer: uart3-xfer {
1945 uart3_cts: uart3-cts {
1949 uart3_rts: uart3-rts {
1955 uart4_xfer: uart4-xfer {
1960 uart4_cts: uart4-cts {
1964 uart4_rts: uart4-rts {
1970 otp_pin: otp-pin {
1974 otp_out: otp-out {
1980 pwm0_pin: pwm0-pin {
1986 pwm1_pin: pwm1-pin {
1992 pwm2_pin: pwm2-pin {
1998 pwm3_pin: pwm3-pin {
2004 rgmii_pins: rgmii-pins {
2022 rmii_pins: rmii-pins {
2037 spdif_tx: spdif-tx {