Lines Matching +full:rk3066 +full:- +full:i2s
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
18 interrupt-parent = <&gic>;
51 arm-pmu {
52 compatible = "arm,cortex-a12-pmu";
57 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
61 #address-cells = <1>;
62 #size-cells = <0>;
63 enable-method = "rockchip,rk3066-smp";
68 compatible = "arm,cortex-a12";
71 operating-points-v2 = <&cpu_opp_table>;
72 #cooling-cells = <2>; /* min followed by max */
73 clock-latency = <40000>;
75 dynamic-power-coefficient = <370>;
79 compatible = "arm,cortex-a12";
82 operating-points-v2 = <&cpu_opp_table>;
83 #cooling-cells = <2>; /* min followed by max */
84 clock-latency = <40000>;
86 dynamic-power-coefficient = <370>;
90 compatible = "arm,cortex-a12";
93 operating-points-v2 = <&cpu_opp_table>;
94 #cooling-cells = <2>; /* min followed by max */
95 clock-latency = <40000>;
97 dynamic-power-coefficient = <370>;
101 compatible = "arm,cortex-a12";
104 operating-points-v2 = <&cpu_opp_table>;
105 #cooling-cells = <2>; /* min followed by max */
106 clock-latency = <40000>;
108 dynamic-power-coefficient = <370>;
112 cpu_opp_table: opp-table-0 {
113 compatible = "operating-points-v2";
114 opp-shared;
116 opp-126000000 {
117 opp-hz = /bits/ 64 <126000000>;
118 opp-microvolt = <900000>;
120 opp-216000000 {
121 opp-hz = /bits/ 64 <216000000>;
122 opp-microvolt = <900000>;
124 opp-312000000 {
125 opp-hz = /bits/ 64 <312000000>;
126 opp-microvolt = <900000>;
128 opp-408000000 {
129 opp-hz = /bits/ 64 <408000000>;
130 opp-microvolt = <900000>;
132 opp-600000000 {
133 opp-hz = /bits/ 64 <600000000>;
134 opp-microvolt = <900000>;
136 opp-696000000 {
137 opp-hz = /bits/ 64 <696000000>;
138 opp-microvolt = <950000>;
140 opp-816000000 {
141 opp-hz = /bits/ 64 <816000000>;
142 opp-microvolt = <1000000>;
144 opp-1008000000 {
145 opp-hz = /bits/ 64 <1008000000>;
146 opp-microvolt = <1050000>;
148 opp-1200000000 {
149 opp-hz = /bits/ 64 <1200000000>;
150 opp-microvolt = <1100000>;
152 opp-1416000000 {
153 opp-hz = /bits/ 64 <1416000000>;
154 opp-microvolt = <1200000>;
156 opp-1512000000 {
157 opp-hz = /bits/ 64 <1512000000>;
158 opp-microvolt = <1300000>;
160 opp-1608000000 {
161 opp-hz = /bits/ 64 <1608000000>;
162 opp-microvolt = <1350000>;
166 reserved-memory {
167 #address-cells = <2>;
168 #size-cells = <2>;
181 dma-unusable@fe000000 {
187 compatible = "fixed-clock";
188 clock-frequency = <24000000>;
189 clock-output-names = "xin24m";
190 #clock-cells = <0>;
194 compatible = "arm,armv7-timer";
195 arm,cpu-registers-not-fw-configured;
200 clock-frequency = <24000000>;
201 arm,no-tick-in-suspend;
205 compatible = "rockchip,rk3288-timer";
209 clock-names = "pclk", "timer";
212 display-subsystem {
213 compatible = "rockchip,display-subsystem";
218 compatible = "rockchip,rk3288-dw-mshc";
219 max-frequency = <150000000>;
222 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
223 fifo-depth = <0x100>;
227 reset-names = "reset";
232 compatible = "rockchip,rk3288-dw-mshc";
233 max-frequency = <150000000>;
236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
237 fifo-depth = <0x100>;
241 reset-names = "reset";
246 compatible = "rockchip,rk3288-dw-mshc";
247 max-frequency = <150000000>;
250 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
251 fifo-depth = <0x100>;
255 reset-names = "reset";
260 compatible = "rockchip,rk3288-dw-mshc";
261 max-frequency = <150000000>;
264 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
265 fifo-depth = <0x100>;
269 reset-names = "reset";
277 #io-channel-cells = <1>;
279 clock-names = "saradc", "apb_pclk";
281 reset-names = "saradc-apb";
286 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
288 clock-names = "spiclk", "apb_pclk";
290 dma-names = "tx", "rx";
292 pinctrl-names = "default";
293 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
295 #address-cells = <1>;
296 #size-cells = <0>;
301 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
303 clock-names = "spiclk", "apb_pclk";
305 dma-names = "tx", "rx";
307 pinctrl-names = "default";
308 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
310 #address-cells = <1>;
311 #size-cells = <0>;
316 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
318 clock-names = "spiclk", "apb_pclk";
320 dma-names = "tx", "rx";
322 pinctrl-names = "default";
323 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
325 #address-cells = <1>;
326 #size-cells = <0>;
331 compatible = "rockchip,rk3288-i2c";
334 #address-cells = <1>;
335 #size-cells = <0>;
336 clock-names = "i2c";
338 pinctrl-names = "default";
339 pinctrl-0 = <&i2c1_xfer>;
344 compatible = "rockchip,rk3288-i2c";
347 #address-cells = <1>;
348 #size-cells = <0>;
349 clock-names = "i2c";
351 pinctrl-names = "default";
352 pinctrl-0 = <&i2c3_xfer>;
357 compatible = "rockchip,rk3288-i2c";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 clock-names = "i2c";
364 pinctrl-names = "default";
365 pinctrl-0 = <&i2c4_xfer>;
370 compatible = "rockchip,rk3288-i2c";
373 #address-cells = <1>;
374 #size-cells = <0>;
375 clock-names = "i2c";
377 pinctrl-names = "default";
378 pinctrl-0 = <&i2c5_xfer>;
383 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
386 reg-shift = <2>;
387 reg-io-width = <4>;
389 clock-names = "baudclk", "apb_pclk";
391 dma-names = "tx", "rx";
392 pinctrl-names = "default";
393 pinctrl-0 = <&uart0_xfer>;
398 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
401 reg-shift = <2>;
402 reg-io-width = <4>;
404 clock-names = "baudclk", "apb_pclk";
406 dma-names = "tx", "rx";
407 pinctrl-names = "default";
408 pinctrl-0 = <&uart1_xfer>;
413 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
416 reg-shift = <2>;
417 reg-io-width = <4>;
419 clock-names = "baudclk", "apb_pclk";
420 pinctrl-names = "default";
421 pinctrl-0 = <&uart2_xfer>;
426 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
429 reg-shift = <2>;
430 reg-io-width = <4>;
432 clock-names = "baudclk", "apb_pclk";
434 dma-names = "tx", "rx";
435 pinctrl-names = "default";
436 pinctrl-0 = <&uart3_xfer>;
441 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
444 reg-shift = <2>;
445 reg-io-width = <4>;
447 clock-names = "baudclk", "apb_pclk";
449 dma-names = "tx", "rx";
450 pinctrl-names = "default";
451 pinctrl-0 = <&uart4_xfer>;
455 dmac_peri: dma-controller@ff250000 {
460 #dma-cells = <1>;
461 arm,pl330-broken-no-flushp;
462 arm,pl330-periph-burst;
464 clock-names = "apb_pclk";
467 thermal-zones {
468 reserve_thermal: reserve-thermal {
469 polling-delay-passive = <1000>; /* milliseconds */
470 polling-delay = <5000>; /* milliseconds */
472 thermal-sensors = <&tsadc 0>;
475 cpu_thermal: cpu-thermal {
476 polling-delay-passive = <100>; /* milliseconds */
477 polling-delay = <5000>; /* milliseconds */
479 thermal-sensors = <&tsadc 1>;
499 cooling-maps {
502 cooling-device =
510 cooling-device =
519 gpu_thermal: gpu-thermal {
520 polling-delay-passive = <100>; /* milliseconds */
521 polling-delay = <5000>; /* milliseconds */
523 thermal-sensors = <&tsadc 2>;
538 cooling-maps {
541 cooling-device =
549 compatible = "rockchip,rk3288-tsadc";
553 clock-names = "tsadc", "apb_pclk";
555 reset-names = "tsadc-apb";
556 pinctrl-names = "init", "default", "sleep";
557 pinctrl-0 = <&otp_pin>;
558 pinctrl-1 = <&otp_out>;
559 pinctrl-2 = <&otp_pin>;
560 #thermal-sensor-cells = <1>;
562 rockchip,hw-tshut-temp = <95000>;
567 compatible = "rockchip,rk3288-gmac";
571 interrupt-names = "macirq", "eth_wake_irq";
577 clock-names = "stmmaceth",
582 reset-names = "stmmaceth";
587 compatible = "generic-ehci";
592 phy-names = "usb";
598 compatible = "generic-ohci";
603 phy-names = "usb";
608 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
613 clock-names = "otg";
616 phy-names = "usb2-phy";
617 snps,reset-phy-on-wake;
622 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
627 clock-names = "otg";
629 g-np-tx-fifo-size = <16>;
630 g-rx-fifo-size = <275>;
631 g-tx-fifo-size = <256 128 128 64 64 32>;
633 phy-names = "usb2-phy";
638 compatible = "generic-ehci";
645 dmac_bus_ns: dma-controller@ff600000 {
650 #dma-cells = <1>;
651 arm,pl330-broken-no-flushp;
652 arm,pl330-periph-burst;
654 clock-names = "apb_pclk";
659 compatible = "rockchip,rk3288-i2c";
662 #address-cells = <1>;
663 #size-cells = <0>;
664 clock-names = "i2c";
666 pinctrl-names = "default";
667 pinctrl-0 = <&i2c0_xfer>;
672 compatible = "rockchip,rk3288-i2c";
675 #address-cells = <1>;
676 #size-cells = <0>;
677 clock-names = "i2c";
679 pinctrl-names = "default";
680 pinctrl-0 = <&i2c2_xfer>;
685 compatible = "rockchip,rk3288-pwm";
687 #pwm-cells = <3>;
688 pinctrl-names = "default";
689 pinctrl-0 = <&pwm0_pin>;
695 compatible = "rockchip,rk3288-pwm";
697 #pwm-cells = <3>;
698 pinctrl-names = "default";
699 pinctrl-0 = <&pwm1_pin>;
705 compatible = "rockchip,rk3288-pwm";
707 #pwm-cells = <3>;
708 pinctrl-names = "default";
709 pinctrl-0 = <&pwm2_pin>;
715 compatible = "rockchip,rk3288-pwm";
717 #pwm-cells = <3>;
718 pinctrl-names = "default";
719 pinctrl-0 = <&pwm3_pin>;
725 compatible = "mmio-sram";
727 #address-cells = <1>;
728 #size-cells = <1>;
730 smp-sram@0 {
731 compatible = "rockchip,rk3066-smp-sram";
737 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
741 pmu: power-management@ff730000 {
742 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
745 power: power-controller {
746 compatible = "rockchip,rk3288-power-controller";
747 #power-domain-cells = <1>;
748 #address-cells = <1>;
749 #size-cells = <0>;
751 assigned-clocks = <&cru SCLK_EDP_24M>;
752 assigned-clock-parents = <&xin24m>;
777 power-domain@RK3288_PD_VIO {
813 #power-domain-cells = <0>;
820 power-domain@RK3288_PD_HEVC {
827 #power-domain-cells = <0>;
835 power-domain@RK3288_PD_VIDEO {
840 #power-domain-cells = <0>;
847 power-domain@RK3288_PD_GPU {
852 #power-domain-cells = <0>;
856 reboot-mode {
857 compatible = "syscon-reboot-mode";
859 mode-normal = <BOOT_NORMAL>;
860 mode-recovery = <BOOT_RECOVERY>;
861 mode-bootloader = <BOOT_FASTBOOT>;
862 mode-loader = <BOOT_BL_DOWNLOAD>;
867 compatible = "rockchip,rk3288-sgrf", "syscon";
871 cru: clock-controller@ff760000 {
872 compatible = "rockchip,rk3288-cru";
875 clock-names = "xin24m";
877 #clock-cells = <1>;
878 #reset-cells = <1>;
879 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
884 assigned-clock-rates = <594000000>, <400000000>,
892 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
895 edp_phy: edp-phy {
896 compatible = "rockchip,rk3288-dp-phy";
898 clock-names = "24m";
899 #phy-cells = <0>;
903 io_domains: io-domains {
904 compatible = "rockchip,rk3288-io-voltage-domain";
909 compatible = "rockchip,rk3288-usb-phy";
910 #address-cells = <1>;
911 #size-cells = <0>;
914 usbphy0: usb-phy@320 {
915 #phy-cells = <0>;
918 clock-names = "phyclk";
919 #clock-cells = <0>;
921 reset-names = "phy-reset";
924 usbphy1: usb-phy@334 {
925 #phy-cells = <0>;
928 clock-names = "phyclk";
929 #clock-cells = <0>;
931 reset-names = "phy-reset";
934 usbphy2: usb-phy@348 {
935 #phy-cells = <0>;
938 clock-names = "phyclk";
939 #clock-cells = <0>;
941 reset-names = "phy-reset";
947 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
955 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
957 #sound-dai-cells = <0>;
959 clock-names = "mclk", "hclk";
961 dma-names = "tx";
963 pinctrl-names = "default";
964 pinctrl-0 = <&spdif_tx>;
969 i2s: i2s@ff890000 { label
970 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
972 #sound-dai-cells = <0>;
975 clock-names = "i2s_clk", "i2s_hclk";
977 dma-names = "tx", "rx";
978 pinctrl-names = "default";
979 pinctrl-0 = <&i2s0_bus>;
980 rockchip,playback-channels = <8>;
981 rockchip,capture-channels = <2>;
986 compatible = "rockchip,rk3288-crypto";
991 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
993 reset-names = "crypto-rst";
1001 clock-names = "aclk", "iface";
1002 #iommu-cells = <0>;
1011 clock-names = "aclk", "iface";
1012 #iommu-cells = <0>;
1013 rockchip,disable-mmu-reset;
1018 compatible = "rockchip,rk3288-rga";
1022 clock-names = "aclk", "hclk", "sclk";
1023 power-domains = <&power RK3288_PD_VIO>;
1025 reset-names = "core", "axi", "ahb";
1029 compatible = "rockchip,rk3288-vop";
1033 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1034 power-domains = <&power RK3288_PD_VIO>;
1036 reset-names = "axi", "ahb", "dclk";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1046 remote-endpoint = <&hdmi_in_vopb>;
1051 remote-endpoint = <&edp_in_vopb>;
1056 remote-endpoint = <&mipi_in_vopb>;
1061 remote-endpoint = <&lvds_in_vopb>;
1071 clock-names = "aclk", "iface";
1072 power-domains = <&power RK3288_PD_VIO>;
1073 #iommu-cells = <0>;
1078 compatible = "rockchip,rk3288-vop";
1082 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1083 power-domains = <&power RK3288_PD_VIO>;
1085 reset-names = "axi", "ahb", "dclk";
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1095 remote-endpoint = <&hdmi_in_vopl>;
1100 remote-endpoint = <&edp_in_vopl>;
1105 remote-endpoint = <&mipi_in_vopl>;
1110 remote-endpoint = <&lvds_in_vopl>;
1120 clock-names = "aclk", "iface";
1121 power-domains = <&power RK3288_PD_VIO>;
1122 #iommu-cells = <0>;
1127 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1131 clock-names = "ref", "pclk";
1132 power-domains = <&power RK3288_PD_VIO>;
1137 #address-cells = <1>;
1138 #size-cells = <0>;
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1147 remote-endpoint = <&vopb_out_mipi>;
1152 remote-endpoint = <&vopl_out_mipi>;
1163 compatible = "rockchip,rk3288-lvds";
1166 clock-names = "pclk_lvds";
1167 pinctrl-names = "lcdc";
1168 pinctrl-0 = <&lcdc_ctl>;
1169 power-domains = <&power RK3288_PD_VIO>;
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1179 #address-cells = <1>;
1180 #size-cells = <0>;
1184 remote-endpoint = <&vopb_out_lvds>;
1189 remote-endpoint = <&vopl_out_lvds>;
1200 compatible = "rockchip,rk3288-dp";
1204 clock-names = "dp", "pclk";
1206 phy-names = "dp";
1207 power-domains = <&power RK3288_PD_VIO>;
1209 reset-names = "dp";
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1224 remote-endpoint = <&vopb_out_edp>;
1229 remote-endpoint = <&vopl_out_edp>;
1240 compatible = "rockchip,rk3288-dw-hdmi";
1242 reg-io-width = <4>;
1245 clock-names = "iahb", "isfr", "cec";
1246 power-domains = <&power RK3288_PD_VIO>;
1248 #sound-dai-cells = <0>;
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1262 remote-endpoint = <&vopb_out_hdmi>;
1267 remote-endpoint = <&vopl_out_hdmi>;
1277 vpu: video-codec@ff9a0000 {
1278 compatible = "rockchip,rk3288-vpu";
1282 interrupt-names = "vepu", "vdpu";
1284 clock-names = "aclk", "hclk";
1286 power-domains = <&power RK3288_PD_VIDEO>;
1294 clock-names = "aclk", "iface";
1295 #iommu-cells = <0>;
1296 power-domains = <&power RK3288_PD_VIDEO>;
1304 clock-names = "aclk", "iface";
1305 #iommu-cells = <0>;
1310 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1315 interrupt-names = "job", "mmu", "gpu";
1317 operating-points-v2 = <&gpu_opp_table>;
1318 #cooling-cells = <2>; /* min followed by max */
1319 power-domains = <&power RK3288_PD_GPU>;
1323 gpu_opp_table: opp-table-1 {
1324 compatible = "operating-points-v2";
1326 opp-100000000 {
1327 opp-hz = /bits/ 64 <100000000>;
1328 opp-microvolt = <950000>;
1330 opp-200000000 {
1331 opp-hz = /bits/ 64 <200000000>;
1332 opp-microvolt = <950000>;
1334 opp-300000000 {
1335 opp-hz = /bits/ 64 <300000000>;
1336 opp-microvolt = <1000000>;
1338 opp-400000000 {
1339 opp-hz = /bits/ 64 <400000000>;
1340 opp-microvolt = <1100000>;
1342 opp-600000000 {
1343 opp-hz = /bits/ 64 <600000000>;
1344 opp-microvolt = <1250000>;
1349 compatible = "rockchip,rk3288-qos", "syscon";
1354 compatible = "rockchip,rk3288-qos", "syscon";
1359 compatible = "rockchip,rk3288-qos", "syscon";
1364 compatible = "rockchip,rk3288-qos", "syscon";
1369 compatible = "rockchip,rk3288-qos", "syscon";
1374 compatible = "rockchip,rk3288-qos", "syscon";
1379 compatible = "rockchip,rk3288-qos", "syscon";
1384 compatible = "rockchip,rk3288-qos", "syscon";
1389 compatible = "rockchip,rk3288-qos", "syscon";
1394 compatible = "rockchip,rk3288-qos", "syscon";
1399 compatible = "rockchip,rk3288-qos", "syscon";
1404 compatible = "rockchip,rk3288-qos", "syscon";
1409 compatible = "rockchip,rk3288-qos", "syscon";
1414 compatible = "rockchip,rk3288-qos", "syscon";
1418 dmac_bus_s: dma-controller@ffb20000 {
1423 #dma-cells = <1>;
1424 arm,pl330-broken-no-flushp;
1425 arm,pl330-periph-burst;
1427 clock-names = "apb_pclk";
1431 compatible = "rockchip,rk3288-efuse";
1433 #address-cells = <1>;
1434 #size-cells = <1>;
1436 clock-names = "pclk_efuse";
1438 cpu_id: cpu-id@7 {
1446 gic: interrupt-controller@ffc01000 {
1447 compatible = "arm,gic-400";
1448 interrupt-controller;
1449 #interrupt-cells = <3>;
1450 #address-cells = <0>;
1460 compatible = "rockchip,rk3288-pinctrl";
1463 #address-cells = <2>;
1464 #size-cells = <2>;
1468 compatible = "rockchip,gpio-bank";
1473 gpio-controller;
1474 #gpio-cells = <2>;
1476 interrupt-controller;
1477 #interrupt-cells = <2>;
1481 compatible = "rockchip,gpio-bank";
1486 gpio-controller;
1487 #gpio-cells = <2>;
1489 interrupt-controller;
1490 #interrupt-cells = <2>;
1494 compatible = "rockchip,gpio-bank";
1499 gpio-controller;
1500 #gpio-cells = <2>;
1502 interrupt-controller;
1503 #interrupt-cells = <2>;
1507 compatible = "rockchip,gpio-bank";
1512 gpio-controller;
1513 #gpio-cells = <2>;
1515 interrupt-controller;
1516 #interrupt-cells = <2>;
1520 compatible = "rockchip,gpio-bank";
1525 gpio-controller;
1526 #gpio-cells = <2>;
1528 interrupt-controller;
1529 #interrupt-cells = <2>;
1533 compatible = "rockchip,gpio-bank";
1538 gpio-controller;
1539 #gpio-cells = <2>;
1541 interrupt-controller;
1542 #interrupt-cells = <2>;
1546 compatible = "rockchip,gpio-bank";
1551 gpio-controller;
1552 #gpio-cells = <2>;
1554 interrupt-controller;
1555 #interrupt-cells = <2>;
1559 compatible = "rockchip,gpio-bank";
1564 gpio-controller;
1565 #gpio-cells = <2>;
1567 interrupt-controller;
1568 #interrupt-cells = <2>;
1572 compatible = "rockchip,gpio-bank";
1577 gpio-controller;
1578 #gpio-cells = <2>;
1580 interrupt-controller;
1581 #interrupt-cells = <2>;
1585 hdmi_cec_c0: hdmi-cec-c0 {
1589 hdmi_cec_c7: hdmi-cec-c7 {
1593 hdmi_ddc: hdmi-ddc {
1598 hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1604 pcfg_output_low: pcfg-output-low {
1605 output-low;
1608 pcfg_pull_up: pcfg-pull-up {
1609 bias-pull-up;
1612 pcfg_pull_down: pcfg-pull-down {
1613 bias-pull-down;
1616 pcfg_pull_none: pcfg-pull-none {
1617 bias-disable;
1620 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1621 bias-disable;
1622 drive-strength = <12>;
1626 global_pwroff: global-pwroff {
1630 ddrio_pwroff: ddrio-pwroff {
1634 ddr0_retention: ddr0-retention {
1638 ddr1_retention: ddr1-retention {
1644 edp_hpd: edp-hpd {
1650 i2c0_xfer: i2c0-xfer {
1657 i2c1_xfer: i2c1-xfer {
1664 i2c2_xfer: i2c2-xfer {
1671 i2c3_xfer: i2c3-xfer {
1678 i2c4_xfer: i2c4-xfer {
1685 i2c5_xfer: i2c5-xfer {
1692 i2s0_bus: i2s0-bus {
1703 lcdc_ctl: lcdc-ctl {
1712 sdmmc_clk: sdmmc-clk {
1716 sdmmc_cmd: sdmmc-cmd {
1720 sdmmc_cd: sdmmc-cd {
1724 sdmmc_bus1: sdmmc-bus1 {
1728 sdmmc_bus4: sdmmc-bus4 {
1737 sdio0_bus1: sdio0-bus1 {
1741 sdio0_bus4: sdio0-bus4 {
1748 sdio0_cmd: sdio0-cmd {
1752 sdio0_clk: sdio0-clk {
1756 sdio0_cd: sdio0-cd {
1760 sdio0_wp: sdio0-wp {
1764 sdio0_pwr: sdio0-pwr {
1768 sdio0_bkpwr: sdio0-bkpwr {
1772 sdio0_int: sdio0-int {
1778 sdio1_bus1: sdio1-bus1 {
1782 sdio1_bus4: sdio1-bus4 {
1789 sdio1_cd: sdio1-cd {
1793 sdio1_wp: sdio1-wp {
1797 sdio1_bkpwr: sdio1-bkpwr {
1801 sdio1_int: sdio1-int {
1805 sdio1_cmd: sdio1-cmd {
1809 sdio1_clk: sdio1-clk {
1813 sdio1_pwr: sdio1-pwr {
1819 emmc_clk: emmc-clk {
1823 emmc_cmd: emmc-cmd {
1827 emmc_pwr: emmc-pwr {
1831 emmc_bus1: emmc-bus1 {
1835 emmc_bus4: emmc-bus4 {
1842 emmc_bus8: emmc-bus8 {
1855 spi0_clk: spi0-clk {
1858 spi0_cs0: spi0-cs0 {
1861 spi0_tx: spi0-tx {
1864 spi0_rx: spi0-rx {
1867 spi0_cs1: spi0-cs1 {
1872 spi1_clk: spi1-clk {
1875 spi1_cs0: spi1-cs0 {
1878 spi1_rx: spi1-rx {
1881 spi1_tx: spi1-tx {
1887 spi2_cs1: spi2-cs1 {
1890 spi2_clk: spi2-clk {
1893 spi2_cs0: spi2-cs0 {
1896 spi2_rx: spi2-rx {
1899 spi2_tx: spi2-tx {
1905 uart0_xfer: uart0-xfer {
1910 uart0_cts: uart0-cts {
1914 uart0_rts: uart0-rts {
1920 uart1_xfer: uart1-xfer {
1925 uart1_cts: uart1-cts {
1929 uart1_rts: uart1-rts {
1935 uart2_xfer: uart2-xfer {
1943 uart3_xfer: uart3-xfer {
1948 uart3_cts: uart3-cts {
1952 uart3_rts: uart3-rts {
1958 uart4_xfer: uart4-xfer {
1963 uart4_cts: uart4-cts {
1967 uart4_rts: uart4-rts {
1973 otp_pin: otp-pin {
1977 otp_out: otp-out {
1983 pwm0_pin: pwm0-pin {
1989 pwm1_pin: pwm1-pin {
1995 pwm2_pin: pwm2-pin {
2001 pwm3_pin: pwm3-pin {
2007 rgmii_pins: rgmii-pins {
2025 rmii_pins: rmii-pins {
2040 spdif_tx: spdif-tx {