Lines Matching +full:0 +full:xffa30000
62 #size-cells = <0>;
69 reg = <0x500>;
79 reg = <0x501>;
89 reg = <0x502>;
99 reg = <0x503>;
108 cpu_opp_table: opp-table-0 {
169 * The rk3288 cannot use the memory area above 0xfe000000
179 reg = <0x0 0xfe000000 0x0 0x1000000>;
187 #clock-cells = <0>;
203 reg = <0x0 0xff810000 0x0 0x20>;
220 fifo-depth = <0x100>;
222 reg = <0x0 0xff0c0000 0x0 0x4000>;
234 fifo-depth = <0x100>;
236 reg = <0x0 0xff0d0000 0x0 0x4000>;
248 fifo-depth = <0x100>;
250 reg = <0x0 0xff0e0000 0x0 0x4000>;
262 fifo-depth = <0x100>;
264 reg = <0x0 0xff0f0000 0x0 0x4000>;
272 reg = <0x0 0xff100000 0x0 0x100>;
290 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
291 reg = <0x0 0xff110000 0x0 0x1000>;
293 #size-cells = <0>;
305 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
306 reg = <0x0 0xff120000 0x0 0x1000>;
308 #size-cells = <0>;
320 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
321 reg = <0x0 0xff130000 0x0 0x1000>;
323 #size-cells = <0>;
329 reg = <0x0 0xff140000 0x0 0x1000>;
332 #size-cells = <0>;
336 pinctrl-0 = <&i2c1_xfer>;
342 reg = <0x0 0xff150000 0x0 0x1000>;
345 #size-cells = <0>;
349 pinctrl-0 = <&i2c3_xfer>;
355 reg = <0x0 0xff160000 0x0 0x1000>;
358 #size-cells = <0>;
362 pinctrl-0 = <&i2c4_xfer>;
368 reg = <0x0 0xff170000 0x0 0x1000>;
371 #size-cells = <0>;
375 pinctrl-0 = <&i2c5_xfer>;
381 reg = <0x0 0xff180000 0x0 0x100>;
390 pinctrl-0 = <&uart0_xfer>;
396 reg = <0x0 0xff190000 0x0 0x100>;
405 pinctrl-0 = <&uart1_xfer>;
411 reg = <0x0 0xff690000 0x0 0x100>;
418 pinctrl-0 = <&uart2_xfer>;
424 reg = <0x0 0xff1b0000 0x0 0x100>;
433 pinctrl-0 = <&uart3_xfer>;
439 reg = <0x0 0xff1c0000 0x0 0x100>;
448 pinctrl-0 = <&uart4_xfer>;
454 reg = <0x0 0xff250000 0x0 0x4000>;
469 thermal-sensors = <&tsadc 0>;
547 reg = <0x0 0xff280000 0x0 0x100>;
554 pinctrl-0 = <&otp_pin>;
565 reg = <0x0 0xff290000 0x0 0x10000>;
585 reg = <0x0 0xff500000 0x0 0x100>;
596 reg = <0x0 0xff520000 0x0 0x100>;
607 reg = <0x0 0xff540000 0x0 0x40000>;
621 reg = <0x0 0xff580000 0x0 0x40000>;
636 reg = <0x0 0xff5c0000 0x0 0x100>;
644 reg = <0x0 0xff600000 0x0 0x4000>;
645 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
657 reg = <0x0 0xff650000 0x0 0x1000>;
660 #size-cells = <0>;
664 pinctrl-0 = <&i2c0_xfer>;
670 reg = <0x0 0xff660000 0x0 0x1000>;
673 #size-cells = <0>;
677 pinctrl-0 = <&i2c2_xfer>;
683 reg = <0x0 0xff680000 0x0 0x10>;
686 pinctrl-0 = <&pwm0_pin>;
693 reg = <0x0 0xff680010 0x0 0x10>;
696 pinctrl-0 = <&pwm1_pin>;
703 reg = <0x0 0xff680020 0x0 0x10>;
706 pinctrl-0 = <&pwm2_pin>;
713 reg = <0x0 0xff680030 0x0 0x10>;
716 pinctrl-0 = <&pwm3_pin>;
723 reg = <0x0 0xff700000 0x0 0x18000>;
726 ranges = <0 0x0 0xff700000 0x18000>;
727 smp-sram@0 {
729 reg = <0x00 0x10>;
735 reg = <0x0 0xff720000 0x0 0x1000>;
740 reg = <0x0 0xff730000 0x0 0x100>;
746 #size-cells = <0>;
810 #power-domain-cells = <0>;
824 #power-domain-cells = <0>;
837 #power-domain-cells = <0>;
849 #power-domain-cells = <0>;
855 offset = <0x94>;
865 reg = <0x0 0xff740000 0x0 0x1000>;
870 reg = <0x0 0xff760000 0x0 0x1000>;
890 reg = <0x0 0xff770000 0x0 0x1000>;
896 #phy-cells = <0>;
908 #size-cells = <0>;
912 #phy-cells = <0>;
913 reg = <0x320>;
916 #clock-cells = <0>;
922 #phy-cells = <0>;
923 reg = <0x334>;
926 #clock-cells = <0>;
932 #phy-cells = <0>;
933 reg = <0x348>;
936 #clock-cells = <0>;
945 reg = <0x0 0xff800000 0x0 0x100>;
953 reg = <0x0 0xff8b0000 0x0 0x10000>;
954 #sound-dai-cells = <0>;
961 pinctrl-0 = <&spdif_tx>;
968 reg = <0x0 0xff890000 0x0 0x10000>;
969 #sound-dai-cells = <0>;
973 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
976 pinctrl-0 = <&i2s0_bus>;
984 reg = <0x0 0xff8a0000 0x0 0x4000>;
995 reg = <0x0 0xff900800 0x0 0x40>;
999 #iommu-cells = <0>;
1005 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1009 #iommu-cells = <0>;
1016 reg = <0x0 0xff920000 0x0 0x180>;
1027 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
1039 #size-cells = <0>;
1041 vopb_out_hdmi: endpoint@0 {
1042 reg = <0>;
1065 reg = <0x0 0xff930300 0x0 0x100>;
1070 #iommu-cells = <0>;
1076 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
1088 #size-cells = <0>;
1090 vopl_out_hdmi: endpoint@0 {
1091 reg = <0>;
1114 reg = <0x0 0xff940300 0x0 0x100>;
1119 #iommu-cells = <0>;
1125 reg = <0x0 0xff960000 0x0 0x4000>;
1135 #size-cells = <0>;
1137 mipi_in: port@0 {
1138 reg = <0>;
1140 #size-cells = <0>;
1142 mipi_in_vopb: endpoint@0 {
1143 reg = <0>;
1161 reg = <0x0 0xff96c000 0x0 0x4000>;
1165 pinctrl-0 = <&lcdc_ctl>;
1172 #size-cells = <0>;
1174 lvds_in: port@0 {
1175 reg = <0>;
1177 #size-cells = <0>;
1179 lvds_in_vopb: endpoint@0 {
1180 reg = <0>;
1198 reg = <0x0 0xff970000 0x0 0x4000>;
1212 #size-cells = <0>;
1214 edp_in: port@0 {
1215 reg = <0>;
1217 #size-cells = <0>;
1219 edp_in_vopb: endpoint@0 {
1220 reg = <0>;
1238 reg = <0x0 0xff980000 0x0 0x20000>;
1245 #sound-dai-cells = <0>;
1250 #size-cells = <0>;
1252 hdmi_in: port@0 {
1253 reg = <0>;
1255 #size-cells = <0>;
1257 hdmi_in_vopb: endpoint@0 {
1258 reg = <0>;
1276 reg = <0x0 0xff9a0000 0x0 0x800>;
1288 reg = <0x0 0xff9a0800 0x0 0x100>;
1292 #iommu-cells = <0>;
1298 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1302 #iommu-cells = <0>;
1308 reg = <0x0 0xffa30000 0x0 0x10000>;
1347 reg = <0x0 0xffaa0000 0x0 0x20>;
1352 reg = <0x0 0xffaa0080 0x0 0x20>;
1357 reg = <0x0 0xffad0000 0x0 0x20>;
1362 reg = <0x0 0xffad0100 0x0 0x20>;
1367 reg = <0x0 0xffad0180 0x0 0x20>;
1372 reg = <0x0 0xffad0400 0x0 0x20>;
1377 reg = <0x0 0xffad0480 0x0 0x20>;
1382 reg = <0x0 0xffad0500 0x0 0x20>;
1387 reg = <0x0 0xffad0800 0x0 0x20>;
1392 reg = <0x0 0xffad0880 0x0 0x20>;
1397 reg = <0x0 0xffad0900 0x0 0x20>;
1402 reg = <0x0 0xffae0000 0x0 0x20>;
1407 reg = <0x0 0xffaf0000 0x0 0x20>;
1412 reg = <0x0 0xffaf0080 0x0 0x20>;
1417 reg = <0x0 0xffb20000 0x0 0x4000>;
1418 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
1429 reg = <0x0 0xffb40000 0x0 0x20>;
1436 reg = <0x07 0x10>;
1439 reg = <0x17 0x1>;
1447 #address-cells = <0>;
1449 reg = <0x0 0xffc01000 0x0 0x1000>,
1450 <0x0 0xffc02000 0x0 0x2000>,
1451 <0x0 0xffc04000 0x0 0x2000>,
1452 <0x0 0xffc06000 0x0 0x2000>;
1453 interrupts = <GIC_PPI 9 0xf04>;
1466 reg = <0x0 0xff750000 0x0 0x100>;
1479 reg = <0x0 0xff780000 0x0 0x100>;
1492 reg = <0x0 0xff790000 0x0 0x100>;
1505 reg = <0x0 0xff7a0000 0x0 0x100>;
1518 reg = <0x0 0xff7b0000 0x0 0x100>;
1531 reg = <0x0 0xff7c0000 0x0 0x100>;
1544 reg = <0x0 0xff7d0000 0x0 0x100>;
1557 reg = <0x0 0xff7e0000 0x0 0x100>;
1570 reg = <0x0 0xff7f0000 0x0 0x100>;
1624 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
1628 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
1632 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
1636 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
1648 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
1649 <0 RK_PC0 1 &pcfg_pull_none>;
1971 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1975 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;