Lines Matching +full:ns +full:- +full:cru
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
9 #include <dt-bindings/power/rk3228-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
36 resets = <&cru SRST_CORE0>;
37 operating-points-v2 = <&cpu0_opp_table>;
38 #cooling-cells = <2>; /* min followed by max */
39 clocks = <&cru ARMCLK>;
40 enable-method = "psci";
45 compatible = "arm,cortex-a7";
47 resets = <&cru SRST_CORE1>;
48 operating-points-v2 = <&cpu0_opp_table>;
49 #cooling-cells = <2>; /* min followed by max */
50 enable-method = "psci";
55 compatible = "arm,cortex-a7";
57 resets = <&cru SRST_CORE2>;
58 operating-points-v2 = <&cpu0_opp_table>;
59 #cooling-cells = <2>; /* min followed by max */
60 enable-method = "psci";
65 compatible = "arm,cortex-a7";
67 resets = <&cru SRST_CORE3>;
68 operating-points-v2 = <&cpu0_opp_table>;
69 #cooling-cells = <2>; /* min followed by max */
70 enable-method = "psci";
74 cpu0_opp_table: opp-table-0 {
75 compatible = "operating-points-v2";
76 opp-shared;
78 opp-408000000 {
79 opp-hz = /bits/ 64 <408000000>;
80 opp-microvolt = <950000>;
81 clock-latency-ns = <40000>;
82 opp-suspend;
84 opp-600000000 {
85 opp-hz = /bits/ 64 <600000000>;
86 opp-microvolt = <975000>;
88 opp-816000000 {
89 opp-hz = /bits/ 64 <816000000>;
90 opp-microvolt = <1000000>;
92 opp-1008000000 {
93 opp-hz = /bits/ 64 <1008000000>;
94 opp-microvolt = <1175000>;
96 opp-1200000000 {
97 opp-hz = /bits/ 64 <1200000000>;
98 opp-microvolt = <1275000>;
102 arm-pmu {
103 compatible = "arm,cortex-a7-pmu";
108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
112 compatible = "arm,psci-1.0", "arm,psci-0.2";
117 compatible = "arm,armv7-timer";
118 arm,cpu-registers-not-fw-configured;
123 clock-frequency = <24000000>;
127 compatible = "fixed-clock";
128 clock-frequency = <24000000>;
129 clock-output-names = "xin24m";
130 #clock-cells = <0>;
133 display_subsystem: display-subsystem {
134 compatible = "rockchip,display-subsystem";
139 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
142 clock-names = "i2s_clk", "i2s_hclk";
143 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
145 dma-names = "tx", "rx";
146 pinctrl-names = "default";
147 pinctrl-0 = <&i2s1_bus>;
152 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
155 clock-names = "i2s_clk", "i2s_hclk";
156 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
158 dma-names = "tx", "rx";
163 compatible = "rockchip,rk3228-spdif";
166 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
167 clock-names = "mclk", "hclk";
169 dma-names = "tx";
170 pinctrl-names = "default";
171 pinctrl-0 = <&spdif_tx>;
176 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
179 clock-names = "i2s_clk", "i2s_hclk";
180 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
182 dma-names = "tx", "rx";
187 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
189 #address-cells = <1>;
190 #size-cells = <1>;
192 io_domains: io-domains {
193 compatible = "rockchip,rk3228-io-voltage-domain";
197 power: power-controller {
198 compatible = "rockchip,rk3228-power-controller";
199 #power-domain-cells = <1>;
200 #address-cells = <1>;
201 #size-cells = <0>;
203 power-domain@RK3228_PD_VIO {
205 clocks = <&cru ACLK_HDCP>,
206 <&cru SCLK_HDCP>,
207 <&cru ACLK_IEP>,
208 <&cru HCLK_IEP>,
209 <&cru ACLK_RGA>,
210 <&cru HCLK_RGA>,
211 <&cru SCLK_RGA>;
216 #power-domain-cells = <0>;
219 power-domain@RK3228_PD_VOP {
221 clocks = <&cru ACLK_VOP>,
222 <&cru DCLK_VOP>,
223 <&cru HCLK_VOP>;
225 #power-domain-cells = <0>;
228 power-domain@RK3228_PD_VPU {
230 clocks = <&cru ACLK_VPU>,
231 <&cru HCLK_VPU>;
233 #power-domain-cells = <0>;
236 power-domain@RK3228_PD_RKVDEC {
238 clocks = <&cru ACLK_RKVDEC>,
239 <&cru HCLK_RKVDEC>,
240 <&cru SCLK_VDEC_CABAC>,
241 <&cru SCLK_VDEC_CORE>;
244 #power-domain-cells = <0>;
247 power-domain@RK3228_PD_GPU {
249 clocks = <&cru ACLK_GPU>;
251 #power-domain-cells = <0>;
256 compatible = "rockchip,rk3228-usb2phy";
258 clocks = <&cru SCLK_OTGPHY0>;
259 clock-names = "phyclk";
260 clock-output-names = "usb480m_phy0";
261 #clock-cells = <0>;
264 u2phy0_otg: otg-port {
268 interrupt-names = "otg-bvalid", "otg-id",
270 #phy-cells = <0>;
274 u2phy0_host: host-port {
276 interrupt-names = "linestate";
277 #phy-cells = <0>;
283 compatible = "rockchip,rk3228-usb2phy";
285 clocks = <&cru SCLK_OTGPHY1>;
286 clock-names = "phyclk";
287 clock-output-names = "usb480m_phy1";
288 #clock-cells = <0>;
291 u2phy1_otg: otg-port {
293 interrupt-names = "linestate";
294 #phy-cells = <0>;
298 u2phy1_host: host-port {
300 interrupt-names = "linestate";
301 #phy-cells = <0>;
308 compatible = "snps,dw-apb-uart";
311 clock-frequency = <24000000>;
312 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
313 clock-names = "baudclk", "apb_pclk";
314 pinctrl-names = "default";
315 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
316 reg-shift = <2>;
317 reg-io-width = <4>;
322 compatible = "snps,dw-apb-uart";
325 clock-frequency = <24000000>;
326 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
327 clock-names = "baudclk", "apb_pclk";
328 pinctrl-names = "default";
329 pinctrl-0 = <&uart1_xfer>;
330 reg-shift = <2>;
331 reg-io-width = <4>;
336 compatible = "snps,dw-apb-uart";
339 clock-frequency = <24000000>;
340 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
341 clock-names = "baudclk", "apb_pclk";
342 pinctrl-names = "default";
343 pinctrl-0 = <&uart2_xfer>;
344 reg-shift = <2>;
345 reg-io-width = <4>;
350 compatible = "rockchip,rk3228-efuse";
352 clocks = <&cru PCLK_EFUSE_256>;
353 clock-names = "pclk_efuse";
354 #address-cells = <1>;
355 #size-cells = <1>;
367 compatible = "rockchip,rk3228-i2c";
370 #address-cells = <1>;
371 #size-cells = <0>;
372 clock-names = "i2c";
373 clocks = <&cru PCLK_I2C0>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&i2c0_xfer>;
380 compatible = "rockchip,rk3228-i2c";
383 #address-cells = <1>;
384 #size-cells = <0>;
385 clock-names = "i2c";
386 clocks = <&cru PCLK_I2C1>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&i2c1_xfer>;
393 compatible = "rockchip,rk3228-i2c";
396 #address-cells = <1>;
397 #size-cells = <0>;
398 clock-names = "i2c";
399 clocks = <&cru PCLK_I2C2>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&i2c2_xfer>;
406 compatible = "rockchip,rk3228-i2c";
409 #address-cells = <1>;
410 #size-cells = <0>;
411 clock-names = "i2c";
412 clocks = <&cru PCLK_I2C3>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&i2c3_xfer>;
419 compatible = "rockchip,rk3228-spi";
422 #address-cells = <1>;
423 #size-cells = <0>;
424 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
425 clock-names = "spiclk", "apb_pclk";
426 pinctrl-names = "default";
427 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
432 compatible = "rockchip,rk3228-wdt", "snps,dw-wdt";
435 clocks = <&cru PCLK_CPU>;
440 compatible = "rockchip,rk3288-pwm";
442 #pwm-cells = <3>;
443 clocks = <&cru PCLK_PWM>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&pwm0_pin>;
450 compatible = "rockchip,rk3288-pwm";
452 #pwm-cells = <3>;
453 clocks = <&cru PCLK_PWM>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&pwm1_pin>;
460 compatible = "rockchip,rk3288-pwm";
462 #pwm-cells = <3>;
463 clocks = <&cru PCLK_PWM>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&pwm2_pin>;
470 compatible = "rockchip,rk3288-pwm";
472 #pwm-cells = <2>;
473 clocks = <&cru PCLK_PWM>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&pwm3_pin>;
480 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
483 clocks = <&cru PCLK_TIMER>, <&xin24m>;
484 clock-names = "pclk", "timer";
487 cru: clock-controller@110e0000 { label
488 compatible = "rockchip,rk3228-cru";
491 clock-names = "xin24m";
493 #clock-cells = <1>;
494 #reset-cells = <1>;
495 assigned-clocks =
496 <&cru PLL_GPLL>, <&cru ARMCLK>,
497 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
498 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
499 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
500 <&cru PCLK_CPU>;
501 assigned-clock-rates =
509 pdma: dma-controller@110f0000 {
514 #dma-cells = <1>;
515 arm,pl330-periph-burst;
516 clocks = <&cru ACLK_DMAC>;
517 clock-names = "apb_pclk";
520 thermal-zones {
521 cpu_thermal: cpu-thermal {
522 polling-delay-passive = <100>; /* milliseconds */
523 polling-delay = <5000>; /* milliseconds */
525 thermal-sensors = <&tsadc 0>;
545 cooling-maps {
548 cooling-device =
556 cooling-device =
567 compatible = "rockchip,rk3228-tsadc";
570 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
571 clock-names = "tsadc", "apb_pclk";
572 assigned-clocks = <&cru SCLK_TSADC>;
573 assigned-clock-rates = <32768>;
574 resets = <&cru SRST_TSADC>;
575 reset-names = "tsadc-apb";
576 pinctrl-names = "init", "default", "sleep";
577 pinctrl-0 = <&otp_pin>;
578 pinctrl-1 = <&otp_out>;
579 pinctrl-2 = <&otp_pin>;
580 #thermal-sensor-cells = <1>;
581 rockchip,hw-tshut-temp = <95000>;
585 hdmi_phy: hdmi-phy@12030000 {
586 compatible = "rockchip,rk3228-hdmi-phy";
588 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
589 clock-names = "sysclk", "refoclk", "refpclk";
590 #clock-cells = <0>;
591 clock-output-names = "hdmiphy_phy";
592 #phy-cells = <0>;
597 compatible = "rockchip,rk3228-mali", "arm,mali-400";
605 interrupt-names = "gp",
611 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
612 clock-names = "bus", "core";
613 power-domains = <&power RK3228_PD_GPU>;
614 resets = <&cru SRST_GPU_A>;
618 vpu: video-codec@20020000 {
619 compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
623 interrupt-names = "vepu", "vdpu";
624 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
625 clock-names = "aclk", "hclk";
627 power-domains = <&power RK3228_PD_VPU>;
634 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
635 clock-names = "aclk", "iface";
636 power-domains = <&power RK3228_PD_VPU>;
637 #iommu-cells = <0>;
640 vdec: video-codec@20030000 {
641 compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";
644 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
645 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
646 clock-names = "axi", "ahb", "cabac", "core";
647 assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
648 assigned-clock-rates = <300000000>, <300000000>;
650 power-domains = <&power RK3228_PD_RKVDEC>;
657 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
658 clock-names = "aclk", "iface";
659 power-domains = <&power RK3228_PD_RKVDEC>;
660 #iommu-cells = <0>;
664 compatible = "rockchip,rk3228-vop";
667 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
668 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
669 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
670 reset-names = "axi", "ahb", "dclk";
672 power-domains = <&power RK3228_PD_VOP>;
676 #address-cells = <1>;
677 #size-cells = <0>;
681 remote-endpoint = <&hdmi_in_vop>;
690 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
691 clock-names = "aclk", "iface";
692 power-domains = <&power RK3228_PD_VOP>;
693 #iommu-cells = <0>;
698 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
701 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
702 clock-names = "aclk", "hclk", "sclk";
703 power-domains = <&power RK3228_PD_VIO>;
704 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
705 reset-names = "core", "axi", "ahb";
712 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
713 clock-names = "aclk", "iface";
714 power-domains = <&power RK3228_PD_VIO>;
715 #iommu-cells = <0>;
720 compatible = "rockchip,rk3228-dw-hdmi";
722 reg-io-width = <4>;
724 assigned-clocks = <&cru SCLK_HDMI_PHY>;
725 assigned-clock-parents = <&hdmi_phy>;
726 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
727 clock-names = "iahb", "isfr", "cec";
728 pinctrl-names = "default";
729 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
730 resets = <&cru SRST_HDMI_P>;
731 reset-names = "hdmi";
733 phy-names = "hdmi";
738 #address-cells = <1>;
739 #size-cells = <0>;
745 remote-endpoint = <&vop_out_hdmi>;
756 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
759 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
760 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
761 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
762 fifo-depth = <0x100>;
763 pinctrl-names = "default";
764 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
769 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
772 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
773 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
774 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
775 fifo-depth = <0x100>;
776 pinctrl-names = "default";
777 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
782 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
785 clock-frequency = <37500000>;
786 max-frequency = <37500000>;
787 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
788 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
789 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
790 bus-width = <8>;
791 rockchip,default-sample-phase = <158>;
792 fifo-depth = <0x100>;
793 pinctrl-names = "default";
794 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
795 resets = <&cru SRST_EMMC>;
796 reset-names = "reset";
801 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
805 clocks = <&cru HCLK_OTG>;
806 clock-names = "otg";
808 g-np-tx-fifo-size = <16>;
809 g-rx-fifo-size = <280>;
810 g-tx-fifo-size = <256 128 128 64 32 16>;
812 phy-names = "usb2-phy";
817 compatible = "generic-ehci";
820 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
822 phy-names = "usb";
827 compatible = "generic-ohci";
830 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
832 phy-names = "usb";
837 compatible = "generic-ehci";
840 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
842 phy-names = "usb";
847 compatible = "generic-ohci";
850 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
852 phy-names = "usb";
857 compatible = "generic-ehci";
860 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
862 phy-names = "usb";
867 compatible = "generic-ohci";
870 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
872 phy-names = "usb";
877 compatible = "rockchip,rk3228-gmac";
880 interrupt-names = "macirq";
881 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
882 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
883 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
884 <&cru PCLK_GMAC>;
885 clock-names = "stmmaceth", "mac_clk_rx",
889 resets = <&cru SRST_GMAC>;
890 reset-names = "stmmaceth";
896 compatible = "rockchip,rk3228-qos", "syscon";
901 compatible = "rockchip,rk3228-qos", "syscon";
906 compatible = "rockchip,rk3228-qos", "syscon";
911 compatible = "rockchip,rk3228-qos", "syscon";
916 compatible = "rockchip,rk3228-qos", "syscon";
921 compatible = "rockchip,rk3228-qos", "syscon";
926 compatible = "rockchip,rk3228-qos", "syscon";
931 compatible = "rockchip,rk3228-qos", "syscon";
936 compatible = "rockchip,rk3228-qos", "syscon";
940 gic: interrupt-controller@32010000 {
941 compatible = "arm,gic-400";
942 interrupt-controller;
943 #interrupt-cells = <3>;
944 #address-cells = <0>;
954 compatible = "rockchip,rk3228-pinctrl";
956 #address-cells = <1>;
957 #size-cells = <1>;
961 compatible = "rockchip,gpio-bank";
964 clocks = <&cru PCLK_GPIO0>;
966 gpio-controller;
967 #gpio-cells = <2>;
969 interrupt-controller;
970 #interrupt-cells = <2>;
974 compatible = "rockchip,gpio-bank";
977 clocks = <&cru PCLK_GPIO1>;
979 gpio-controller;
980 #gpio-cells = <2>;
982 interrupt-controller;
983 #interrupt-cells = <2>;
987 compatible = "rockchip,gpio-bank";
990 clocks = <&cru PCLK_GPIO2>;
992 gpio-controller;
993 #gpio-cells = <2>;
995 interrupt-controller;
996 #interrupt-cells = <2>;
1000 compatible = "rockchip,gpio-bank";
1003 clocks = <&cru PCLK_GPIO3>;
1005 gpio-controller;
1006 #gpio-cells = <2>;
1008 interrupt-controller;
1009 #interrupt-cells = <2>;
1012 pcfg_pull_up: pcfg-pull-up {
1013 bias-pull-up;
1016 pcfg_pull_down: pcfg-pull-down {
1017 bias-pull-down;
1020 pcfg_pull_none: pcfg-pull-none {
1021 bias-disable;
1024 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1025 drive-strength = <12>;
1029 sdmmc_clk: sdmmc-clk {
1033 sdmmc_cmd: sdmmc-cmd {
1037 sdmmc_bus4: sdmmc-bus4 {
1046 sdio_clk: sdio-clk {
1050 sdio_cmd: sdio-cmd {
1054 sdio_bus4: sdio-bus4 {
1063 emmc_clk: emmc-clk {
1067 emmc_cmd: emmc-cmd {
1071 emmc_bus8: emmc-bus8 {
1084 rgmii_pins: rgmii-pins {
1102 rmii_pins: rmii-pins {
1115 phy_pins: phy-pins {
1122 hdmi_hpd: hdmi-hpd {
1126 hdmii2c_xfer: hdmii2c-xfer {
1131 hdmi_cec: hdmi-cec {
1137 i2c0_xfer: i2c0-xfer {
1144 i2c1_xfer: i2c1-xfer {
1151 i2c2_xfer: i2c2-xfer {
1158 i2c3_xfer: i2c3-xfer {
1165 spi0_clk: spi0-clk {
1168 spi0_cs0: spi0-cs0 {
1171 spi0_tx: spi0-tx {
1174 spi0_rx: spi0-rx {
1177 spi0_cs1: spi0-cs1 {
1183 spi1_clk: spi1-clk {
1186 spi1_cs0: spi1-cs0 {
1189 spi1_rx: spi1-rx {
1192 spi1_tx: spi1-tx {
1195 spi1_cs1: spi1-cs1 {
1201 i2s1_bus: i2s1-bus {
1215 pwm0_pin: pwm0-pin {
1221 pwm1_pin: pwm1-pin {
1227 pwm2_pin: pwm2-pin {
1233 pwm3_pin: pwm3-pin {
1239 spdif_tx: spdif-tx {
1245 otp_pin: otp-pin {
1249 otp_out: otp-out {
1255 uart0_xfer: uart0-xfer {
1260 uart0_cts: uart0-cts {
1264 uart0_rts: uart0-rts {
1270 uart1_xfer: uart1-xfer {
1275 uart1_cts: uart1-cts {
1279 uart1_rts: uart1-rts {
1285 uart2_xfer: uart2-xfer {
1290 uart21_xfer: uart21-xfer {
1295 uart2_cts: uart2-cts {
1299 uart2_rts: uart2-rts {