Lines Matching +full:0 +full:x20030000
30 #size-cells = <0>;
35 reg = <0xf00>;
47 reg = <0xf01>;
57 reg = <0xf02>;
67 reg = <0xf03>;
75 cpu0_opp_table: opp-table-0 {
131 #clock-cells = <0>;
141 reg = <0x100b0000 0x4000>;
148 pinctrl-0 = <&i2s1_bus>;
154 reg = <0x100c0000 0x4000>;
165 reg = <0x100d0000 0x1000>;
172 pinctrl-0 = <&spdif_tx>;
178 reg = <0x100e0000 0x4000>;
182 dmas = <&pdma 0>, <&pdma 1>;
189 reg = <0x11000000 0x1000>;
202 #size-cells = <0>;
217 #power-domain-cells = <0>;
226 #power-domain-cells = <0>;
234 #power-domain-cells = <0>;
245 #power-domain-cells = <0>;
252 #power-domain-cells = <0>;
258 reg = <0x0760 0x0c>;
262 #clock-cells = <0>;
271 #phy-cells = <0>;
278 #phy-cells = <0>;
285 reg = <0x0800 0x0c>;
289 #clock-cells = <0>;
295 #phy-cells = <0>;
302 #phy-cells = <0>;
310 reg = <0x11010000 0x100>;
316 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
324 reg = <0x11020000 0x100>;
330 pinctrl-0 = <&uart1_xfer>;
338 reg = <0x11030000 0x100>;
344 pinctrl-0 = <&uart2_xfer>;
352 reg = <0x11040000 0x20>;
360 reg = <0x7 0x10>;
363 reg = <0x17 0x1>;
369 reg = <0x11050000 0x1000>;
372 #size-cells = <0>;
376 pinctrl-0 = <&i2c0_xfer>;
382 reg = <0x11060000 0x1000>;
385 #size-cells = <0>;
389 pinctrl-0 = <&i2c1_xfer>;
395 reg = <0x11070000 0x1000>;
398 #size-cells = <0>;
402 pinctrl-0 = <&i2c2_xfer>;
408 reg = <0x11080000 0x1000>;
411 #size-cells = <0>;
415 pinctrl-0 = <&i2c3_xfer>;
421 reg = <0x11090000 0x1000>;
424 #size-cells = <0>;
428 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
434 reg = <0x110a0000 0x100>;
442 reg = <0x110b0000 0x10>;
446 pinctrl-0 = <&pwm0_pin>;
452 reg = <0x110b0010 0x10>;
456 pinctrl-0 = <&pwm1_pin>;
462 reg = <0x110b0020 0x10>;
466 pinctrl-0 = <&pwm2_pin>;
472 reg = <0x110b0030 0x10>;
476 pinctrl-0 = <&pwm3_pin>;
482 reg = <0x110c0000 0x20>;
490 reg = <0x110e0000 0x1000>;
512 reg = <0x110f0000 0x4000>;
513 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
526 thermal-sensors = <&tsadc 0>;
569 reg = <0x11150000 0x100>;
578 pinctrl-0 = <&otp_pin>;
588 reg = <0x12030000 0x10000>;
591 #clock-cells = <0>;
593 #phy-cells = <0>;
599 reg = <0x20000000 0x10000>;
621 reg = <0x20020000 0x800>;
633 reg = <0x20020800 0x100>;
638 #iommu-cells = <0>;
643 reg = <0x20030000 0x480>;
656 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
661 #iommu-cells = <0>;
666 reg = <0x20050000 0x1ffc>;
678 #size-cells = <0>;
680 vop_out_hdmi: endpoint@0 {
681 reg = <0>;
689 reg = <0x20053f00 0x100>;
694 #iommu-cells = <0>;
700 reg = <0x20060000 0x1000>;
711 reg = <0x20070800 0x100>;
716 #iommu-cells = <0>;
722 reg = <0x200a0000 0x20000>;
730 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
740 #size-cells = <0>;
742 hdmi_in: port@0 {
743 reg = <0>;
758 reg = <0x30000000 0x4000>;
763 fifo-depth = <0x100>;
765 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
771 reg = <0x30010000 0x4000>;
776 fifo-depth = <0x100>;
778 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
784 reg = <0x30020000 0x4000>;
793 fifo-depth = <0x100>;
795 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
804 reg = <0x30040000 0x40000>;
819 reg = <0x30080000 0x20000>;
829 reg = <0x300a0000 0x20000>;
839 reg = <0x300c0000 0x20000>;
849 reg = <0x300e0000 0x20000>;
859 reg = <0x30100000 0x20000>;
869 reg = <0x30120000 0x20000>;
879 reg = <0x30200000 0x10000>;
898 reg = <0x31030080 0x20>;
903 reg = <0x31030100 0x20>;
908 reg = <0x31030180 0x20>;
913 reg = <0x31030200 0x20>;
918 reg = <0x31040000 0x20>;
923 reg = <0x31050000 0x20>;
928 reg = <0x31060000 0x20>;
933 reg = <0x31070000 0x20>;
938 reg = <0x31070080 0x20>;
945 #address-cells = <0>;
947 reg = <0x32011000 0x1000>,
948 <0x32012000 0x2000>,
949 <0x32014000 0x2000>,
950 <0x32016000 0x2000>;
963 reg = <0x11110000 0x100>;
976 reg = <0x11120000 0x100>;
989 reg = <0x11130000 0x100>;
1002 reg = <0x11140000 0x100>;
1124 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
1128 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1129 <0 RK_PA7 2 &pcfg_pull_none>;
1133 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1139 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1140 <0 RK_PA1 1 &pcfg_pull_none>;
1146 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1147 <0 RK_PA3 1 &pcfg_pull_none>;
1160 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1161 <0 RK_PA7 1 &pcfg_pull_none>;
1167 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1170 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1173 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1176 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1185 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1203 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1204 <0 RK_PB1 1 &pcfg_pull_none>,
1205 <0 RK_PB3 1 &pcfg_pull_none>,
1206 <0 RK_PB4 1 &pcfg_pull_none>,
1207 <0 RK_PB5 1 &pcfg_pull_none>,
1208 <0 RK_PB6 1 &pcfg_pull_none>,
1223 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1247 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1251 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1266 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1297 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1301 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;