Lines Matching +full:0 +full:x110a0000
30 #size-cells = <0>;
35 reg = <0xf00>;
46 reg = <0xf01>;
56 reg = <0xf02>;
66 reg = <0xf03>;
74 cpu0_opp_table: opp-table-0 {
130 #clock-cells = <0>;
140 reg = <0x100b0000 0x4000>;
147 pinctrl-0 = <&i2s1_bus>;
153 reg = <0x100c0000 0x4000>;
164 reg = <0x100d0000 0x1000>;
171 pinctrl-0 = <&spdif_tx>;
177 reg = <0x100e0000 0x4000>;
181 dmas = <&pdma 0>, <&pdma 1>;
188 reg = <0x11000000 0x1000>;
201 #size-cells = <0>;
216 #power-domain-cells = <0>;
225 #power-domain-cells = <0>;
233 #power-domain-cells = <0>;
244 #power-domain-cells = <0>;
251 #power-domain-cells = <0>;
257 reg = <0x0760 0x0c>;
261 #clock-cells = <0>;
270 #phy-cells = <0>;
277 #phy-cells = <0>;
284 reg = <0x0800 0x0c>;
288 #clock-cells = <0>;
294 #phy-cells = <0>;
301 #phy-cells = <0>;
309 reg = <0x11010000 0x100>;
315 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
323 reg = <0x11020000 0x100>;
329 pinctrl-0 = <&uart1_xfer>;
337 reg = <0x11030000 0x100>;
343 pinctrl-0 = <&uart2_xfer>;
351 reg = <0x11040000 0x20>;
359 reg = <0x7 0x10>;
362 reg = <0x17 0x1>;
368 reg = <0x11050000 0x1000>;
371 #size-cells = <0>;
375 pinctrl-0 = <&i2c0_xfer>;
381 reg = <0x11060000 0x1000>;
384 #size-cells = <0>;
388 pinctrl-0 = <&i2c1_xfer>;
394 reg = <0x11070000 0x1000>;
397 #size-cells = <0>;
401 pinctrl-0 = <&i2c2_xfer>;
407 reg = <0x11080000 0x1000>;
410 #size-cells = <0>;
414 pinctrl-0 = <&i2c3_xfer>;
420 reg = <0x11090000 0x1000>;
423 #size-cells = <0>;
427 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
433 reg = <0x110a0000 0x100>;
441 reg = <0x110b0000 0x10>;
445 pinctrl-0 = <&pwm0_pin>;
451 reg = <0x110b0010 0x10>;
455 pinctrl-0 = <&pwm1_pin>;
461 reg = <0x110b0020 0x10>;
465 pinctrl-0 = <&pwm2_pin>;
471 reg = <0x110b0030 0x10>;
475 pinctrl-0 = <&pwm3_pin>;
481 reg = <0x110c0000 0x20>;
489 reg = <0x110e0000 0x1000>;
511 reg = <0x110f0000 0x4000>;
512 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
525 thermal-sensors = <&tsadc 0>;
568 reg = <0x11150000 0x100>;
577 pinctrl-0 = <&otp_pin>;
587 reg = <0x12030000 0x10000>;
590 #clock-cells = <0>;
592 #phy-cells = <0>;
598 reg = <0x20000000 0x10000>;
620 reg = <0x20020000 0x800>;
632 reg = <0x20020800 0x100>;
637 #iommu-cells = <0>;
642 reg = <0x20030000 0x480>;
655 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
660 #iommu-cells = <0>;
665 reg = <0x20050000 0x1ffc>;
677 #size-cells = <0>;
679 vop_out_hdmi: endpoint@0 {
680 reg = <0>;
688 reg = <0x20053f00 0x100>;
693 #iommu-cells = <0>;
699 reg = <0x20060000 0x1000>;
710 reg = <0x20070800 0x100>;
715 #iommu-cells = <0>;
721 reg = <0x200a0000 0x20000>;
729 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
739 #size-cells = <0>;
741 hdmi_in: port@0 {
742 reg = <0>;
757 reg = <0x30000000 0x4000>;
762 fifo-depth = <0x100>;
764 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
770 reg = <0x30010000 0x4000>;
775 fifo-depth = <0x100>;
777 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
783 reg = <0x30020000 0x4000>;
792 fifo-depth = <0x100>;
794 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
803 reg = <0x30040000 0x40000>;
818 reg = <0x30080000 0x20000>;
828 reg = <0x300a0000 0x20000>;
838 reg = <0x300c0000 0x20000>;
848 reg = <0x300e0000 0x20000>;
858 reg = <0x30100000 0x20000>;
868 reg = <0x30120000 0x20000>;
878 reg = <0x30200000 0x10000>;
897 reg = <0x31030080 0x20>;
902 reg = <0x31030100 0x20>;
907 reg = <0x31030180 0x20>;
912 reg = <0x31030200 0x20>;
917 reg = <0x31040000 0x20>;
922 reg = <0x31050000 0x20>;
927 reg = <0x31060000 0x20>;
932 reg = <0x31070000 0x20>;
937 reg = <0x31070080 0x20>;
944 #address-cells = <0>;
946 reg = <0x32011000 0x1000>,
947 <0x32012000 0x2000>,
948 <0x32014000 0x2000>,
949 <0x32016000 0x2000>;
962 reg = <0x11110000 0x100>;
975 reg = <0x11120000 0x100>;
988 reg = <0x11130000 0x100>;
1001 reg = <0x11140000 0x100>;
1123 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
1127 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1128 <0 RK_PA7 2 &pcfg_pull_none>;
1132 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1138 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1139 <0 RK_PA1 1 &pcfg_pull_none>;
1145 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1146 <0 RK_PA3 1 &pcfg_pull_none>;
1159 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1160 <0 RK_PA7 1 &pcfg_pull_none>;
1166 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1169 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1172 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1175 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1184 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1202 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1203 <0 RK_PB1 1 &pcfg_pull_none>,
1204 <0 RK_PB3 1 &pcfg_pull_none>,
1205 <0 RK_PB4 1 &pcfg_pull_none>,
1206 <0 RK_PB5 1 &pcfg_pull_none>,
1207 <0 RK_PB6 1 &pcfg_pull_none>,
1222 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1246 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1250 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1265 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1296 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1300 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;