Lines Matching +full:cru +full:- +full:bus
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
26 clocks = <&cru ARMCLK>;
27 operating-points-v2 = <&cpu0_opp_table>;
28 resets = <&cru SRST_CORE0>;
32 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
35 operating-points-v2 = <&cpu0_opp_table>;
36 resets = <&cru SRST_CORE1>;
40 compatible = "arm,cortex-a9";
41 next-level-cache = <&L2>;
43 operating-points-v2 = <&cpu0_opp_table>;
44 resets = <&cru SRST_CORE2>;
48 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
51 operating-points-v2 = <&cpu0_opp_table>;
52 resets = <&cru SRST_CORE3>;
56 cpu0_opp_table: opp-table-0 {
57 compatible = "operating-points-v2";
58 opp-shared;
60 opp-312000000 {
61 opp-hz = /bits/ 64 <312000000>;
62 opp-microvolt = <875000>;
63 clock-latency-ns = <40000>;
65 opp-504000000 {
66 opp-hz = /bits/ 64 <504000000>;
67 opp-microvolt = <925000>;
69 opp-600000000 {
70 opp-hz = /bits/ 64 <600000000>;
71 opp-microvolt = <950000>;
72 opp-suspend;
74 opp-816000000 {
75 opp-hz = /bits/ 64 <816000000>;
76 opp-microvolt = <975000>;
78 opp-1008000000 {
79 opp-hz = /bits/ 64 <1008000000>;
80 opp-microvolt = <1075000>;
82 opp-1200000000 {
83 opp-hz = /bits/ 64 <1200000000>;
84 opp-microvolt = <1150000>;
86 opp-1416000000 {
87 opp-hz = /bits/ 64 <1416000000>;
88 opp-microvolt = <1250000>;
90 opp-1608000000 {
91 opp-hz = /bits/ 64 <1608000000>;
92 opp-microvolt = <1350000>;
96 display-subsystem {
97 compatible = "rockchip,display-subsystem";
102 compatible = "mmio-sram";
104 #address-cells = <1>;
105 #size-cells = <1>;
108 smp-sram@0 {
109 compatible = "rockchip,rk3066-smp-sram";
115 compatible = "rockchip,rk3188-vop";
118 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
119 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
120 power-domains = <&power RK3188_PD_VIO>;
121 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
122 reset-names = "axi", "ahb", "dclk";
126 #address-cells = <1>;
127 #size-cells = <0>;
132 compatible = "rockchip,rk3188-vop";
135 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
136 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
137 power-domains = <&power RK3188_PD_VIO>;
138 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
139 reset-names = "axi", "ahb", "dclk";
143 #address-cells = <1>;
144 #size-cells = <0>;
149 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
152 clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
153 clock-names = "pclk", "timer";
157 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
160 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
161 clock-names = "pclk", "timer";
165 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
168 pinctrl-names = "default";
169 pinctrl-0 = <&i2s0_bus>;
170 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
171 clock-names = "i2s_clk", "i2s_hclk";
173 dma-names = "tx", "rx";
174 rockchip,playback-channels = <2>;
175 rockchip,capture-channels = <2>;
176 #sound-dai-cells = <0>;
181 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
183 #sound-dai-cells = <0>;
184 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
185 clock-names = "mclk", "hclk";
187 dma-names = "tx";
189 pinctrl-names = "default";
190 pinctrl-0 = <&spdif_tx>;
194 cru: clock-controller@20000000 { label
195 compatible = "rockchip,rk3188-cru";
198 clock-names = "xin24m";
200 #clock-cells = <1>;
201 #reset-cells = <1>;
205 compatible = "rockchip,rk3188-efuse";
207 #address-cells = <1>;
208 #size-cells = <1>;
209 clocks = <&cru PCLK_EFUSE>;
210 clock-names = "pclk_efuse";
218 compatible = "rockchip,rk3188-pinctrl";
222 #address-cells = <1>;
223 #size-cells = <1>;
227 compatible = "rockchip,rk3188-gpio-bank0";
230 clocks = <&cru PCLK_GPIO0>;
232 gpio-controller;
233 #gpio-cells = <2>;
235 interrupt-controller;
236 #interrupt-cells = <2>;
240 compatible = "rockchip,gpio-bank";
243 clocks = <&cru PCLK_GPIO1>;
245 gpio-controller;
246 #gpio-cells = <2>;
248 interrupt-controller;
249 #interrupt-cells = <2>;
253 compatible = "rockchip,gpio-bank";
256 clocks = <&cru PCLK_GPIO2>;
258 gpio-controller;
259 #gpio-cells = <2>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
266 compatible = "rockchip,gpio-bank";
269 clocks = <&cru PCLK_GPIO3>;
271 gpio-controller;
272 #gpio-cells = <2>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
278 pcfg_pull_up: pcfg-pull-up {
279 bias-pull-up;
282 pcfg_pull_down: pcfg-pull-down {
283 bias-pull-down;
286 pcfg_pull_none: pcfg-pull-none {
287 bias-disable;
291 emmc_clk: emmc-clk {
295 emmc_cmd: emmc-cmd {
299 emmc_rst: emmc-rst {
307 * flash/emmc is the boot-device.
312 emac_xfer: emac-xfer {
323 emac_mdio: emac-mdio {
330 i2c0_xfer: i2c0-xfer {
337 i2c1_xfer: i2c1-xfer {
344 i2c2_xfer: i2c2-xfer {
351 i2c3_xfer: i2c3-xfer {
358 i2c4_xfer: i2c4-xfer {
365 lcdc1_dclk: lcdc1-dclk {
369 lcdc1_den: lcdc1-den {
373 lcdc1_hsync: lcdc1-hsync {
377 lcdc1_vsync: lcdc1-vsync {
381 lcdc1_rgb24: lcdc1-rgb24 {
410 pwm0_out: pwm0-out {
416 pwm1_out: pwm1-out {
422 pwm2_out: pwm2-out {
428 pwm3_out: pwm3-out {
434 spi0_clk: spi0-clk {
437 spi0_cs0: spi0-cs0 {
440 spi0_tx: spi0-tx {
443 spi0_rx: spi0-rx {
446 spi0_cs1: spi0-cs1 {
452 spi1_clk: spi1-clk {
455 spi1_cs0: spi1-cs0 {
458 spi1_rx: spi1-rx {
461 spi1_tx: spi1-tx {
464 spi1_cs1: spi1-cs1 {
470 uart0_xfer: uart0-xfer {
475 uart0_cts: uart0-cts {
479 uart0_rts: uart0-rts {
485 uart1_xfer: uart1-xfer {
490 uart1_cts: uart1-cts {
494 uart1_rts: uart1-rts {
500 uart2_xfer: uart2-xfer {
508 uart3_xfer: uart3-xfer {
513 uart3_cts: uart3-cts {
517 uart3_rts: uart3-rts {
523 sd0_clk: sd0-clk {
527 sd0_cmd: sd0-cmd {
531 sd0_cd: sd0-cd {
535 sd0_wp: sd0-wp {
539 sd0_pwr: sd0-pwr {
543 sd0_bus1: sd0-bus-width1 {
547 sd0_bus4: sd0-bus-width4 {
556 sd1_clk: sd1-clk {
560 sd1_cmd: sd1-cmd {
564 sd1_cd: sd1-cd {
568 sd1_wp: sd1-wp {
572 sd1_bus1: sd1-bus-width1 {
576 sd1_bus4: sd1-bus-width4 {
585 i2s0_bus: i2s0-bus {
596 spdif_tx: spdif-tx {
604 compatible = "rockchip,rk3188-emac";
616 compatible = "rockchip,rk3188-mali", "arm,mali-400";
627 interrupt-names = "gp",
637 power-domains = <&power RK3188_PD_GPU>;
641 compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
643 io_domains: io-domains {
644 compatible = "rockchip,rk3188-io-voltage-domain";
649 compatible = "rockchip,rk3188-usb-phy";
650 #address-cells = <1>;
651 #size-cells = <0>;
654 usbphy0: usb-phy@10c {
656 clocks = <&cru SCLK_OTGPHY0>;
657 clock-names = "phyclk";
658 #clock-cells = <0>;
659 #phy-cells = <0>;
662 usbphy1: usb-phy@11c {
664 clocks = <&cru SCLK_OTGPHY1>;
665 clock-names = "phyclk";
666 #clock-cells = <0>;
667 #phy-cells = <0>;
673 compatible = "rockchip,rk3188-i2c";
674 pinctrl-names = "default";
675 pinctrl-0 = <&i2c0_xfer>;
679 compatible = "rockchip,rk3188-i2c";
680 pinctrl-names = "default";
681 pinctrl-0 = <&i2c1_xfer>;
685 compatible = "rockchip,rk3188-i2c";
686 pinctrl-names = "default";
687 pinctrl-0 = <&i2c2_xfer>;
691 compatible = "rockchip,rk3188-i2c";
692 pinctrl-names = "default";
693 pinctrl-0 = <&i2c3_xfer>;
697 compatible = "rockchip,rk3188-i2c";
698 pinctrl-names = "default";
699 pinctrl-0 = <&i2c4_xfer>;
703 power: power-controller {
704 compatible = "rockchip,rk3188-power-controller";
705 #power-domain-cells = <1>;
706 #address-cells = <1>;
707 #size-cells = <0>;
709 power-domain@RK3188_PD_VIO {
711 clocks = <&cru ACLK_LCDC0>,
712 <&cru ACLK_LCDC1>,
713 <&cru DCLK_LCDC0>,
714 <&cru DCLK_LCDC1>,
715 <&cru HCLK_LCDC0>,
716 <&cru HCLK_LCDC1>,
717 <&cru SCLK_CIF0>,
718 <&cru ACLK_CIF0>,
719 <&cru HCLK_CIF0>,
720 <&cru ACLK_IPP>,
721 <&cru HCLK_IPP>,
722 <&cru ACLK_RGA>,
723 <&cru HCLK_RGA>;
729 #power-domain-cells = <0>;
732 power-domain@RK3188_PD_VIDEO {
734 clocks = <&cru ACLK_VDPU>,
735 <&cru ACLK_VEPU>,
736 <&cru HCLK_VDPU>,
737 <&cru HCLK_VEPU>;
739 #power-domain-cells = <0>;
742 power-domain@RK3188_PD_GPU {
744 clocks = <&cru ACLK_GPU>;
746 #power-domain-cells = <0>;
752 pinctrl-names = "default";
753 pinctrl-0 = <&pwm0_out>;
757 pinctrl-names = "default";
758 pinctrl-0 = <&pwm1_out>;
762 pinctrl-names = "default";
763 pinctrl-0 = <&pwm2_out>;
767 pinctrl-names = "default";
768 pinctrl-0 = <&pwm3_out>;
772 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
773 pinctrl-names = "default";
774 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
778 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
779 pinctrl-names = "default";
780 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
784 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
785 pinctrl-names = "default";
786 pinctrl-0 = <&uart0_xfer>;
790 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
791 pinctrl-names = "default";
792 pinctrl-0 = <&uart1_xfer>;
796 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
797 pinctrl-names = "default";
798 pinctrl-0 = <&uart2_xfer>;
802 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
803 pinctrl-names = "default";
804 pinctrl-0 = <&uart3_xfer>;
808 compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";
809 power-domains = <&power RK3188_PD_VIDEO>;
813 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";