Lines Matching +full:pwm +full:- +full:pins
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
33 arm-pmu {
34 compatible = "arm,cortex-a7-pmu";
39 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
43 #address-cells = <1>;
44 #size-cells = <0>;
45 enable-method = "rockchip,rk3036-smp";
49 compatible = "arm,cortex-a7";
51 clock-latency = <40000>;
54 operating-points-v2 = <&cpu_opp_table>;
55 #cooling-cells = <2>; /* min followed by max */
60 compatible = "arm,cortex-a7";
63 operating-points-v2 = <&cpu_opp_table>;
68 compatible = "arm,cortex-a7";
71 operating-points-v2 = <&cpu_opp_table>;
76 compatible = "arm,cortex-a7";
79 operating-points-v2 = <&cpu_opp_table>;
83 cpu_opp_table: opp-table-0 {
84 compatible = "operating-points-v2";
85 opp-shared;
87 opp-216000000 {
88 opp-hz = /bits/ 64 <216000000>;
89 opp-microvolt = <950000 950000 1325000>;
91 opp-408000000 {
92 opp-hz = /bits/ 64 <408000000>;
93 opp-microvolt = <950000 950000 1325000>;
95 opp-600000000 {
96 opp-hz = /bits/ 64 <600000000>;
97 opp-microvolt = <950000 950000 1325000>;
99 opp-696000000 {
100 opp-hz = /bits/ 64 <696000000>;
101 opp-microvolt = <975000 975000 1325000>;
103 opp-816000000 {
104 opp-hz = /bits/ 64 <816000000>;
105 opp-microvolt = <1075000 1075000 1325000>;
106 opp-suspend;
108 opp-1008000000 {
109 opp-hz = /bits/ 64 <1008000000>;
110 opp-microvolt = <1200000 1200000 1325000>;
112 opp-1200000000 {
113 opp-hz = /bits/ 64 <1200000000>;
114 opp-microvolt = <1325000 1325000 1325000>;
118 display_subsystem: display-subsystem {
119 compatible = "rockchip,display-subsystem";
124 gpu_opp_table: opp-table-1 {
125 compatible = "operating-points-v2";
127 opp-200000000 {
128 opp-hz = /bits/ 64 <200000000>;
129 opp-microvolt = <975000 975000 1250000>;
131 opp-300000000 {
132 opp-hz = /bits/ 64 <300000000>;
133 opp-microvolt = <1050000 1050000 1250000>;
135 opp-400000000 {
136 opp-hz = /bits/ 64 <400000000>;
137 opp-microvolt = <1150000 1150000 1250000>;
139 opp-480000000 {
140 opp-hz = /bits/ 64 <480000000>;
141 opp-microvolt = <1250000 1250000 1250000>;
146 compatible = "arm,armv7-timer";
151 arm,cpu-registers-not-fw-configured;
152 clock-frequency = <24000000>;
156 compatible = "fixed-clock";
157 clock-frequency = <24000000>;
158 clock-output-names = "xin24m";
159 #clock-cells = <0>;
163 compatible = "mmio-sram";
165 #address-cells = <1>;
166 #size-cells = <1>;
169 smp-sram@0 {
170 compatible = "rockchip,rk3066-smp-sram";
176 compatible = "rockchip,rk3128-mali", "arm,mali-400";
184 interrupt-names = "gp",
191 clock-names = "bus", "core";
192 operating-points-v2 = <&gpu_opp_table>;
194 power-domains = <&power RK3128_PD_GPU>;
199 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
202 power: power-controller {
203 compatible = "rockchip,rk3128-power-controller";
204 #power-domain-cells = <1>;
205 #address-cells = <1>;
206 #size-cells = <0>;
208 power-domain@RK3128_PD_VIO {
234 #power-domain-cells = <0>;
237 power-domain@RK3128_PD_VIDEO {
245 #power-domain-cells = <0>;
248 power-domain@RK3128_PD_GPU {
252 #power-domain-cells = <0>;
257 vpu: video-codec@10106000 {
258 compatible = "rockchip,rk3128-vpu", "rockchip,rk3066-vpu";
262 interrupt-names = "vepu", "vdpu";
265 clock-names = "aclk_vdpu", "hclk_vdpu",
268 power-domains = <&power RK3128_PD_VIDEO>;
276 clock-names = "aclk", "iface";
277 power-domains = <&power RK3128_PD_VIDEO>;
278 #iommu-cells = <0>;
282 compatible = "rockchip,rk3126-vop";
287 clock-names = "aclk_vop", "dclk_vop",
291 reset-names = "axi", "ahb",
293 power-domains = <&power RK3128_PD_VIO>;
297 #address-cells = <1>;
298 #size-cells = <0>;
302 remote-endpoint = <&hdmi_in_vop>;
307 remote-endpoint = <&dsi_in_vop>;
313 compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi";
317 clock-names = "pclk";
319 phy-names = "dphy";
320 power-domains = <&power RK3128_PD_VIO>;
322 reset-names = "apb";
327 #address-cells = <1>;
328 #size-cells = <0>;
334 remote-endpoint = <&vop_out_dsi>;
345 compatible = "rockchip,rk3128-qos", "syscon";
350 compatible = "rockchip,rk3128-qos", "syscon";
355 compatible = "rockchip,rk3128-qos", "syscon";
360 compatible = "rockchip,rk3128-qos", "syscon";
365 compatible = "rockchip,rk3128-qos", "syscon";
370 compatible = "rockchip,rk3128-qos", "syscon";
375 compatible = "rockchip,rk3128-qos", "syscon";
379 gic: interrupt-controller@10139000 {
380 compatible = "arm,cortex-a7-gic";
386 interrupt-controller;
387 #interrupt-cells = <3>;
388 #address-cells = <0>;
392 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
396 clock-names = "otg";
398 g-np-tx-fifo-size = <16>;
399 g-rx-fifo-size = <280>;
400 g-tx-fifo-size = <256 128 128 64 32 16>;
402 phy-names = "usb2-phy";
407 compatible = "generic-ehci";
412 phy-names = "usb";
417 compatible = "generic-ohci";
422 phy-names = "usb";
427 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
431 clock-names = "i2s_clk", "i2s_hclk";
433 dma-names = "tx", "rx";
434 #sound-dai-cells = <0>;
439 compatible = "rockchip,rk3128-spdif", "rockchip,rk3066-spdif";
443 clock-names = "mclk", "hclk";
445 dma-names = "tx";
446 pinctrl-names = "default";
447 pinctrl-0 = <&spdif_tx>;
448 #sound-dai-cells = <0>;
457 clock-names = "clk_sfc", "hclk_sfc";
462 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
467 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
469 dma-names = "rx-tx";
470 fifo-depth = <256>;
471 max-frequency = <150000000>;
473 reset-names = "reset";
478 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
483 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
485 dma-names = "rx-tx";
486 fifo-depth = <256>;
487 max-frequency = <150000000>;
489 reset-names = "reset";
494 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
499 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
501 dma-names = "rx-tx";
502 fifo-depth = <256>;
503 max-frequency = <150000000>;
505 reset-names = "reset";
510 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
514 clock-names = "i2s_clk", "i2s_hclk";
516 dma-names = "tx", "rx";
517 rockchip,playback-channels = <2>;
518 pinctrl-names = "default";
519 pinctrl-0 = <&i2s_bus>;
520 #sound-dai-cells = <0>;
524 nfc: nand-controller@10500000 {
525 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
529 clock-names = "ahb", "nfc";
530 pinctrl-names = "default";
531 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
536 cru: clock-controller@20000000 {
537 compatible = "rockchip,rk3128-cru";
540 clock-names = "xin24m";
542 #clock-cells = <1>;
543 #reset-cells = <1>;
544 assigned-clocks = <&cru PLL_GPLL>;
545 assigned-clock-rates = <594000000>;
549 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
551 #address-cells = <1>;
552 #size-cells = <1>;
555 compatible = "rockchip,rk3128-usb2phy";
558 clock-names = "phyclk";
559 clock-output-names = "usb480m_phy";
560 assigned-clocks = <&cru SCLK_USB480M>;
561 assigned-clock-parents = <&usb2phy>;
562 #clock-cells = <0>;
565 usb2phy_host: host-port {
567 interrupt-names = "linestate";
568 #phy-cells = <0>;
572 usb2phy_otg: otg-port {
576 interrupt-names = "otg-bvalid", "otg-id",
578 #phy-cells = <0>;
585 compatible = "rockchip,rk3128-inno-hdmi";
589 clock-names = "pclk", "ref";
590 pinctrl-names = "default";
591 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
592 power-domains = <&power RK3128_PD_VIO>;
593 #sound-dai-cells = <0>;
597 #address-cells = <1>;
598 #size-cells = <0>;
603 remote-endpoint = <&vop_out_hdmi>;
614 compatible = "rockchip,rk3128-dsi-dphy";
617 clock-names = "ref", "pclk";
618 #phy-cells = <0>;
619 power-domains = <&power RK3128_PD_VIO>;
621 reset-names = "apb";
626 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
630 clock-names = "pclk", "timer";
634 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
638 clock-names = "pclk", "timer";
642 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
646 clock-names = "pclk", "timer";
650 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
654 clock-names = "pclk", "timer";
658 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
662 clock-names = "pclk", "timer";
666 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
670 clock-names = "pclk", "timer";
674 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
681 pwm0: pwm@20050000 {
682 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
685 pinctrl-names = "default";
686 pinctrl-0 = <&pwm0_pin>;
687 #pwm-cells = <3>;
691 pwm1: pwm@20050010 {
692 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
695 pinctrl-names = "default";
696 pinctrl-0 = <&pwm1_pin>;
697 #pwm-cells = <3>;
701 pwm2: pwm@20050020 {
702 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
705 pinctrl-names = "default";
706 pinctrl-0 = <&pwm2_pin>;
707 #pwm-cells = <3>;
711 pwm3: pwm@20050030 {
712 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
715 pinctrl-names = "default";
716 pinctrl-0 = <&pwm3_pin>;
717 #pwm-cells = <3>;
722 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
725 clock-names = "i2c";
727 pinctrl-names = "default";
728 pinctrl-0 = <&i2c1_xfer>;
729 #address-cells = <1>;
730 #size-cells = <0>;
735 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
738 clock-names = "i2c";
740 pinctrl-names = "default";
741 pinctrl-0 = <&i2c2_xfer>;
742 #address-cells = <1>;
743 #size-cells = <0>;
748 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
751 clock-names = "i2c";
753 pinctrl-names = "default";
754 pinctrl-0 = <&i2c3_xfer>;
755 #address-cells = <1>;
756 #size-cells = <0>;
761 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
764 clock-frequency = <24000000>;
766 clock-names = "baudclk", "apb_pclk";
768 dma-names = "tx", "rx";
769 pinctrl-names = "default";
770 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
771 reg-io-width = <4>;
772 reg-shift = <2>;
777 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
780 clock-frequency = <24000000>;
782 clock-names = "baudclk", "apb_pclk";
784 dma-names = "tx", "rx";
785 pinctrl-names = "default";
786 pinctrl-0 = <&uart1_xfer>;
787 reg-io-width = <4>;
788 reg-shift = <2>;
793 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
796 clock-frequency = <24000000>;
798 clock-names = "baudclk", "apb_pclk";
800 dma-names = "tx", "rx";
801 pinctrl-names = "default";
802 pinctrl-0 = <&uart2_xfer>;
803 reg-io-width = <4>;
804 reg-shift = <2>;
813 clock-names = "saradc", "apb_pclk";
815 reset-names = "saradc-apb";
816 #io-channel-cells = <1>;
821 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
824 clock-names = "i2c";
826 pinctrl-names = "default";
827 pinctrl-0 = <&i2c0_xfer>;
828 #address-cells = <1>;
829 #size-cells = <0>;
834 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
838 clock-names = "spiclk", "apb_pclk";
840 dma-names = "tx", "rx";
841 pinctrl-names = "default";
842 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
843 #address-cells = <1>;
844 #size-cells = <0>;
848 pdma: dma-controller@20078000 {
853 arm,pl330-broken-no-flushp;
854 arm,pl330-periph-burst;
856 clock-names = "apb_pclk";
857 #dma-cells = <1>;
861 compatible = "rockchip,rk3128-gmac";
865 interrupt-names = "macirq", "eth_wake_irq";
870 clock-names = "stmmaceth",
875 reset-names = "stmmaceth";
877 rx-fifo-depth = <4096>;
878 tx-fifo-depth = <2048>;
882 compatible = "snps,dwmac-mdio";
883 #address-cells = <0x1>;
884 #size-cells = <0x0>;
889 compatible = "rockchip,rk3128-pinctrl";
891 #address-cells = <1>;
892 #size-cells = <1>;
896 compatible = "rockchip,gpio-bank";
900 gpio-controller;
901 #gpio-cells = <2>;
902 interrupt-controller;
903 #interrupt-cells = <2>;
907 compatible = "rockchip,gpio-bank";
911 gpio-controller;
912 #gpio-cells = <2>;
913 interrupt-controller;
914 #interrupt-cells = <2>;
918 compatible = "rockchip,gpio-bank";
922 gpio-controller;
923 #gpio-cells = <2>;
924 interrupt-controller;
925 #interrupt-cells = <2>;
929 compatible = "rockchip,gpio-bank";
933 gpio-controller;
934 #gpio-cells = <2>;
935 interrupt-controller;
936 #interrupt-cells = <2>;
939 pcfg_pull_default: pcfg-pull-default {
940 bias-pull-pin-default;
943 pcfg_pull_none: pcfg-pull-none {
944 bias-disable;
948 emmc_clk: emmc-clk {
949 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
952 emmc_cmd: emmc-cmd {
953 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
956 emmc_cmd1: emmc-cmd1 {
957 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
960 emmc_pwr: emmc-pwr {
961 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
964 emmc_bus1: emmc-bus1 {
965 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
968 emmc_bus4: emmc-bus4 {
969 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
975 emmc_bus8: emmc-bus8 {
976 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
988 rgmii_pins: rgmii-pins {
989 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
1006 rmii_pins: rmii-pins {
1007 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
1021 hdmii2c_xfer: hdmii2c-xfer {
1022 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1026 hdmi_hpd: hdmi-hpd {
1027 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
1030 hdmi_cec: hdmi-cec {
1031 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1036 i2c0_xfer: i2c0-xfer {
1037 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1043 i2c1_xfer: i2c1-xfer {
1044 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1050 i2c2_xfer: i2c2-xfer {
1051 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
1057 i2c3_xfer: i2c3-xfer {
1058 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1064 i2s_bus: i2s-bus {
1065 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1073 i2s1_bus: i2s1-bus {
1074 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
1084 lcdc_dclk: lcdc-dclk {
1085 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>;
1088 lcdc_den: lcdc-den {
1089 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>;
1092 lcdc_hsync: lcdc-hsync {
1093 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1096 lcdc_vsync: lcdc-vsync {
1097 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>;
1100 lcdc_rgb24: lcdc-rgb24 {
1101 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1119 flash_ale: flash-ale {
1120 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>;
1123 flash_cle: flash-cle {
1124 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>;
1127 flash_wrn: flash-wrn {
1128 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1131 flash_rdn: flash-rdn {
1132 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>;
1135 flash_rdy: flash-rdy {
1136 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1139 flash_cs0: flash-cs0 {
1140 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1143 flash_dqs: flash-dqs {
1144 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
1147 flash_bus8: flash-bus8 {
1148 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1160 pwm0_pin: pwm0-pin {
1161 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
1166 pwm1_pin: pwm1-pin {
1167 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1172 pwm2_pin: pwm2-pin {
1173 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1178 pwm3_pin: pwm3-pin {
1179 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
1184 sdio_clk: sdio-clk {
1185 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
1188 sdio_cmd: sdio-cmd {
1189 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
1192 sdio_pwren: sdio-pwren {
1193 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
1196 sdio_bus4: sdio-bus4 {
1197 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
1205 sdmmc_clk: sdmmc-clk {
1206 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
1209 sdmmc_cmd: sdmmc-cmd {
1210 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
1213 sdmmc_det: sdmmc-det {
1214 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
1217 sdmmc_wp: sdmmc-wp {
1218 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
1221 sdmmc_pwren: sdmmc-pwren {
1222 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>;
1225 sdmmc_bus4: sdmmc-bus4 {
1226 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
1234 sfc_bus2: sfc-bus2 {
1235 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
1239 sfc_bus4: sfc-bus4 {
1240 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
1246 sfc_clk: sfc-clk {
1247 rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>;
1250 sfc_cs0: sfc-cs0 {
1251 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_default>;
1254 sfc_cs1: sfc-cs1 {
1255 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_default>;
1260 spdif_tx: spdif-tx {
1261 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
1266 spi0_clk: spi0-clk {
1267 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
1270 spi0_cs0: spi0-cs0 {
1271 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
1274 spi0_tx: spi0-tx {
1275 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
1278 spi0_rx: spi0-rx {
1279 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
1282 spi0_cs1: spi0-cs1 {
1283 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
1286 spi1_clk: spi1-clk {
1287 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
1290 spi1_cs0: spi1-cs0 {
1291 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
1294 spi1_tx: spi1-tx {
1295 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
1298 spi1_rx: spi1-rx {
1299 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
1302 spi1_cs1: spi1-cs1 {
1303 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
1306 spi2_clk: spi2-clk {
1307 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
1310 spi2_cs0: spi2-cs0 {
1311 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
1314 spi2_tx: spi2-tx {
1315 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
1318 spi2_rx: spi2-rx {
1319 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
1324 uart0_xfer: uart0-xfer {
1325 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
1329 uart0_cts: uart0-cts {
1330 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
1333 uart0_rts: uart0-rts {
1334 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
1339 uart1_xfer: uart1-xfer {
1340 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
1344 uart1_cts: uart1-cts {
1345 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
1348 uart1_rts: uart1-rts {
1349 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1354 uart2_xfer: uart2-xfer {
1355 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
1359 uart2_cts: uart2-cts {
1360 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1363 uart2_rts: uart2-rts {
1364 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;